JPS5520541A - Automatic registering system - Google Patents

Automatic registering system

Info

Publication number
JPS5520541A
JPS5520541A JP9289378A JP9289378A JPS5520541A JP S5520541 A JPS5520541 A JP S5520541A JP 9289378 A JP9289378 A JP 9289378A JP 9289378 A JP9289378 A JP 9289378A JP S5520541 A JPS5520541 A JP S5520541A
Authority
JP
Japan
Prior art keywords
department
amount
key
constitution
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9289378A
Other languages
Japanese (ja)
Inventor
Toru Yamakita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP9289378A priority Critical patent/JPS5520541A/en
Publication of JPS5520541A publication Critical patent/JPS5520541A/en
Pending legal-status Critical Current

Links

Landscapes

  • Cash Registers Or Receiving Machines (AREA)

Abstract

PURPOSE: To secure the department-based registering by using the lowest rank digit or the information including the lowest rank digit among the information supplied in a fixed time after operation of the amount key as the department number and the rest as the cash amount respectively.
CONSTITUTION: The memory consisting of RAM is read and written via signal W/R2 of CUP, and the constant switch receives the switch signals through terminal MS of CPU. I/O port 24 is connected to CPU to decide via signal AO whether the information supplied via row address bus CB is the row address or the operation to carry out switching. Buffers 24aW24c are installed to the port and then connected to key input part 25, display part 26 and print part 27 respectively. With operation of the key input, the prescribed operation is given to register and display the amount with every department for printing. In this constitution, both the amount and the department-based designation can be registered all at once via the same amount key. As a result, only the queuing is required until the end of registering, thus enhancing the working efficiency.
COPYRIGHT: (C)1980,JPO&Japio
JP9289378A 1978-07-28 1978-07-28 Automatic registering system Pending JPS5520541A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9289378A JPS5520541A (en) 1978-07-28 1978-07-28 Automatic registering system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9289378A JPS5520541A (en) 1978-07-28 1978-07-28 Automatic registering system

Publications (1)

Publication Number Publication Date
JPS5520541A true JPS5520541A (en) 1980-02-14

Family

ID=14067129

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9289378A Pending JPS5520541A (en) 1978-07-28 1978-07-28 Automatic registering system

Country Status (1)

Country Link
JP (1) JPS5520541A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59151280A (en) * 1983-02-18 1984-08-29 オムロン株式会社 Transaction processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59151280A (en) * 1983-02-18 1984-08-29 オムロン株式会社 Transaction processor

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