JPS5520544A - Coincidence bit counter circuit - Google Patents

Coincidence bit counter circuit

Info

Publication number
JPS5520544A
JPS5520544A JP9291678A JP9291678A JPS5520544A JP S5520544 A JPS5520544 A JP S5520544A JP 9291678 A JP9291678 A JP 9291678A JP 9291678 A JP9291678 A JP 9291678A JP S5520544 A JPS5520544 A JP S5520544A
Authority
JP
Japan
Prior art keywords
terminal
input
bits
full adder
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9291678A
Other languages
Japanese (ja)
Inventor
Tsutomu Iwahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9291678A priority Critical patent/JPS5520544A/en
Publication of JPS5520544A publication Critical patent/JPS5520544A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To constitute the coincidence bit counter circuit with the binary bit parallel full adder of the minimum number by making use the input terminal which is not so far used in the circuit and even carry input terminal CO of the lowest rank bit when necessary as the signal input terminal.
CONSTITUTION: Input signals 1a, 1b and 1c are applied to terminals A1, B1 and C1 by making use of carry input terminal CO of the full adder of the lowest rank bit, and thus 20 bits and 21 bits are obtained at sum output terminal S1 and carry output terminal C1. Input A2 and B2 of the full adder using the output of terminal C1 as the input are earthed to obtain 21 bits through terminal S2. As terminal C2 features the output of zero, A3 and B3 are connected with signal 1a' supplied to obtain output C3. Then signals 1b' and 1c' are supplied to the full adder using C3 as the input, and thus 20 bits and 21 bits are delivered to terminals S4 and C4 each. In this constitution, just one unit of the full adder of n-bits can form (n-1/3)+1 pairs of independent coincidence bit counter circuits of 3 input, thus ensuring an effective use of the multi-bit parallel full adder.
COPYRIGHT: (C)1980,JPO&Japio
JP9291678A 1978-07-28 1978-07-28 Coincidence bit counter circuit Pending JPS5520544A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9291678A JPS5520544A (en) 1978-07-28 1978-07-28 Coincidence bit counter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9291678A JPS5520544A (en) 1978-07-28 1978-07-28 Coincidence bit counter circuit

Publications (1)

Publication Number Publication Date
JPS5520544A true JPS5520544A (en) 1980-02-14

Family

ID=14067799

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9291678A Pending JPS5520544A (en) 1978-07-28 1978-07-28 Coincidence bit counter circuit

Country Status (1)

Country Link
JP (1) JPS5520544A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0713303A2 (en) * 1994-11-15 1996-05-22 Nec Corporation System for detecting non-coincidence of codes

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0713303A2 (en) * 1994-11-15 1996-05-22 Nec Corporation System for detecting non-coincidence of codes

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