JPS5520558A - Clock switching system - Google Patents

Clock switching system

Info

Publication number
JPS5520558A
JPS5520558A JP9334878A JP9334878A JPS5520558A JP S5520558 A JPS5520558 A JP S5520558A JP 9334878 A JP9334878 A JP 9334878A JP 9334878 A JP9334878 A JP 9334878A JP S5520558 A JPS5520558 A JP S5520558A
Authority
JP
Japan
Prior art keywords
several
state
clock
circuit
clocks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9334878A
Other languages
Japanese (ja)
Inventor
Toshitaka Tsuda
Yoshihiro Tomita
Masao Yamazawa
Michinobu Ohata
Toshihiko Matsumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9334878A priority Critical patent/JPS5520558A/en
Publication of JPS5520558A publication Critical patent/JPS5520558A/en
Pending legal-status Critical Current

Links

Landscapes

  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

PURPOSE: To omit the selecting pin by selecting the clock based on the selection information in order to obtain the specified clock from the clock of the several modes.
CONSTITUTION: The selection circuit contains one or several units of control circuit 1 to vary the state of at least one clock among several ones, one or several units of state setting FF2 which sets the state corresponding to the state of several clocks delivered from circuit 1, and gates 3W5 which use several clocks and the output of FF2 as the input. The set state of FF2 is varied by changing the state of at least one clock via circuit 1, and then one of several clocks is delivered selectively.
COPYRIGHT: (C)1980,JPO&Japio
JP9334878A 1978-07-31 1978-07-31 Clock switching system Pending JPS5520558A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9334878A JPS5520558A (en) 1978-07-31 1978-07-31 Clock switching system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9334878A JPS5520558A (en) 1978-07-31 1978-07-31 Clock switching system

Publications (1)

Publication Number Publication Date
JPS5520558A true JPS5520558A (en) 1980-02-14

Family

ID=14079761

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9334878A Pending JPS5520558A (en) 1978-07-31 1978-07-31 Clock switching system

Country Status (1)

Country Link
JP (1) JPS5520558A (en)

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