JPS5524414A - Electrode forming process - Google Patents

Electrode forming process

Info

Publication number
JPS5524414A
JPS5524414A JP9623178A JP9623178A JPS5524414A JP S5524414 A JPS5524414 A JP S5524414A JP 9623178 A JP9623178 A JP 9623178A JP 9623178 A JP9623178 A JP 9623178A JP S5524414 A JPS5524414 A JP S5524414A
Authority
JP
Japan
Prior art keywords
bump
sio
forming process
electrode forming
plated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9623178A
Other languages
Japanese (ja)
Inventor
Toru Kawanobe
Kichiji Inaba
Keiji Miyamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9623178A priority Critical patent/JPS5524414A/en
Publication of JPS5524414A publication Critical patent/JPS5524414A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: To simplify formation of a bump by plating Sn and Pb separately and applying Pb plated layer uppermost which is particularly chemical-resistant.
CONSTITUTION: An Al wiring 3 is provided on Si substrate 1 through SiO2 2, which is covered with SiO2 4. Next, Ti 17 and Cu 18 are spattered, and Ni 20, Sn 21 and Pb 22 are plated in sequence by means of a resist mask 19. The mask 19 is removed, and Cu 18 and Ti 17 are subjected successively to selective etching. After washing and drying, the solder component is melted through heating at 340°C instantaneously. A semiglobular bump 23 is then obtained through surface tension.
COPYRIGHT: (C)1980,JPO&Japio
JP9623178A 1978-08-09 1978-08-09 Electrode forming process Pending JPS5524414A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9623178A JPS5524414A (en) 1978-08-09 1978-08-09 Electrode forming process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9623178A JPS5524414A (en) 1978-08-09 1978-08-09 Electrode forming process

Publications (1)

Publication Number Publication Date
JPS5524414A true JPS5524414A (en) 1980-02-21

Family

ID=14159445

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9623178A Pending JPS5524414A (en) 1978-08-09 1978-08-09 Electrode forming process

Country Status (1)

Country Link
JP (1) JPS5524414A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60130846A (en) * 1983-12-19 1985-07-12 Toshiba Corp Manufacture of bump electrode type semiconductor device
JPS60224248A (en) * 1984-04-23 1985-11-08 Oki Electric Ind Co Ltd Manufacture of semiconductor device
US5151332A (en) * 1986-11-10 1992-09-29 Hazeltine Corporation Aluminum sheets bonded with cadmium
WO1996026808A1 (en) * 1995-03-01 1996-09-06 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Metallised under-layer for (soldering) filler materials
KR100694428B1 (en) * 2000-12-29 2007-03-12 앰코 테크놀로지 코리아 주식회사 Lower bump metallization layer structure of semiconductor chip and manufacturing method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4847273A (en) * 1971-10-15 1973-07-05
JPS5384466A (en) * 1976-12-29 1978-07-25 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4847273A (en) * 1971-10-15 1973-07-05
JPS5384466A (en) * 1976-12-29 1978-07-25 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60130846A (en) * 1983-12-19 1985-07-12 Toshiba Corp Manufacture of bump electrode type semiconductor device
JPS60224248A (en) * 1984-04-23 1985-11-08 Oki Electric Ind Co Ltd Manufacture of semiconductor device
US5151332A (en) * 1986-11-10 1992-09-29 Hazeltine Corporation Aluminum sheets bonded with cadmium
WO1996026808A1 (en) * 1995-03-01 1996-09-06 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Metallised under-layer for (soldering) filler materials
KR100694428B1 (en) * 2000-12-29 2007-03-12 앰코 테크놀로지 코리아 주식회사 Lower bump metallization layer structure of semiconductor chip and manufacturing method thereof

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