JPS5525106A - Main memory control system - Google Patents

Main memory control system

Info

Publication number
JPS5525106A
JPS5525106A JP9677978A JP9677978A JPS5525106A JP S5525106 A JPS5525106 A JP S5525106A JP 9677978 A JP9677978 A JP 9677978A JP 9677978 A JP9677978 A JP 9677978A JP S5525106 A JPS5525106 A JP S5525106A
Authority
JP
Japan
Prior art keywords
main memory
address
bus
memory
mmu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9677978A
Other languages
Japanese (ja)
Inventor
Shigekazu Sumita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP9677978A priority Critical patent/JPS5525106A/en
Publication of JPS5525106A publication Critical patent/JPS5525106A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To obrain an inexpensive main memory control system of high generality and simple constitution by providing a memory interface circuit MI/F to each main memory unit MMU contituting a main memory unit.
CONSTITUTION: Via memory bus 102 and I/O bus 103, CPU is connected to pages O to m-1 composed of main memory unit (MMU) and memory interface (MI/F). Each MI/F has address setting part 201 which sets its own machine address. When the machine address sent from CPU via bus 103 agrees with the above-mentioned address, latch 202 is set and a page address from CPU is set to register 203. When the content of page address setting part 208 agrees with that of register 203, gate 209 is opened and access to MMU can be attained according to the memory address from memory bus 102.
COPYRIGHT: (C)1980,JPO&Japio
JP9677978A 1978-08-09 1978-08-09 Main memory control system Pending JPS5525106A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9677978A JPS5525106A (en) 1978-08-09 1978-08-09 Main memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9677978A JPS5525106A (en) 1978-08-09 1978-08-09 Main memory control system

Publications (1)

Publication Number Publication Date
JPS5525106A true JPS5525106A (en) 1980-02-22

Family

ID=14174113

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9677978A Pending JPS5525106A (en) 1978-08-09 1978-08-09 Main memory control system

Country Status (1)

Country Link
JP (1) JPS5525106A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01200449A (en) * 1988-02-05 1989-08-11 Hitachi Ltd Lsi with chip selecting function
JPH01281544A (en) * 1987-12-18 1989-11-13 Philips Gloeilampenfab:Nv Information processing system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01281544A (en) * 1987-12-18 1989-11-13 Philips Gloeilampenfab:Nv Information processing system
JPH01200449A (en) * 1988-02-05 1989-08-11 Hitachi Ltd Lsi with chip selecting function

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