JPS5525849A - Refresh control circuit - Google Patents

Refresh control circuit

Info

Publication number
JPS5525849A
JPS5525849A JP9826578A JP9826578A JPS5525849A JP S5525849 A JPS5525849 A JP S5525849A JP 9826578 A JP9826578 A JP 9826578A JP 9826578 A JP9826578 A JP 9826578A JP S5525849 A JPS5525849 A JP S5525849A
Authority
JP
Japan
Prior art keywords
signal line
refresh
flop
flip
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9826578A
Other languages
Japanese (ja)
Inventor
Tetsuo Miura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9826578A priority Critical patent/JPS5525849A/en
Publication of JPS5525849A publication Critical patent/JPS5525849A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To decrease the hard quantity necessary for the time supervisory or the like as well as to prevent the performance lowering for the external unit by controlling the refresh based on only the presence or absence of the access given from outside. CONSTITUTION:When an access request is given from the external unit via signal line 12, flip-flop 13 is set and the access request indication signal is transmitted to signal line 16 from output terminal S to discontinue the refresh action of refresh circuit 10. In case no access request is given, flip-flop 13 is reset and the level of logic ''1'' is transmitted to signal line 17 from output terminal R to set flip-flop 14. The clock pulse sent from signal line 11 is supplied to flip-flop 14 from terminal S via delay circuit 15 and signal lime 18, and the refresh action signal is transmitted to signal line 19 from terminal S. Circuit 10 gives advance to the refresh address and gives an access to the memory element via signal line 21.
JP9826578A 1978-08-14 1978-08-14 Refresh control circuit Pending JPS5525849A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9826578A JPS5525849A (en) 1978-08-14 1978-08-14 Refresh control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9826578A JPS5525849A (en) 1978-08-14 1978-08-14 Refresh control circuit

Publications (1)

Publication Number Publication Date
JPS5525849A true JPS5525849A (en) 1980-02-23

Family

ID=14215105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9826578A Pending JPS5525849A (en) 1978-08-14 1978-08-14 Refresh control circuit

Country Status (1)

Country Link
JP (1) JPS5525849A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5722899U (en) * 1980-07-15 1982-02-05

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5421228A (en) * 1977-07-19 1979-02-17 Fujitsu Ltd Refresh system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5421228A (en) * 1977-07-19 1979-02-17 Fujitsu Ltd Refresh system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5722899U (en) * 1980-07-15 1982-02-05

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