JPS5528580A - Memory control circuit - Google Patents

Memory control circuit

Info

Publication number
JPS5528580A
JPS5528580A JP10204578A JP10204578A JPS5528580A JP S5528580 A JPS5528580 A JP S5528580A JP 10204578 A JP10204578 A JP 10204578A JP 10204578 A JP10204578 A JP 10204578A JP S5528580 A JPS5528580 A JP S5528580A
Authority
JP
Japan
Prior art keywords
address
signal
memory
given
decision
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10204578A
Other languages
Japanese (ja)
Inventor
Tsugio Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10204578A priority Critical patent/JPS5528580A/en
Publication of JPS5528580A publication Critical patent/JPS5528580A/en
Pending legal-status Critical Current

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  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To secure an assured switching to the auxiliary memory when the fault occurrence time by controlling the memory through production of the address decision signal with operation between the address and the upper and lower limit addresses.
CONSTITUTION: The address given from address inout buffer 6 is added to the lower and upper limit addresses of lower and upper address decision holding registors 1 and 2 via full adders 3 and 4, and adders 3 and 4 generate the carry signal of the highest-rank bit when the operation result becomes less and more than the lower and upper limit addresses each. And then an addition is given between the carry signal and the decision signal formed by the complements of digital 1 and 2 of lower and upper limit address decision holding registors 1' and 2'. Thus memory selection control signal 10 features a high level only when the address is within the upper and lower limit ranges. As a result, the selection for the auxiliary memory is controlled by signal 10 at the fault occurrence time, and thus the correction, replacement and others can be given to the faulty memory in the state under which other memories are operating.
COPYRIGHT: (C)1980,JPO&Japio
JP10204578A 1978-08-22 1978-08-22 Memory control circuit Pending JPS5528580A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10204578A JPS5528580A (en) 1978-08-22 1978-08-22 Memory control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10204578A JPS5528580A (en) 1978-08-22 1978-08-22 Memory control circuit

Publications (1)

Publication Number Publication Date
JPS5528580A true JPS5528580A (en) 1980-02-29

Family

ID=14316792

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10204578A Pending JPS5528580A (en) 1978-08-22 1978-08-22 Memory control circuit

Country Status (1)

Country Link
JP (1) JPS5528580A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4830332A (en) * 1971-08-18 1973-04-21
JPS5311334A (en) * 1976-07-19 1978-02-01 Toshiba Corp Microwave heater
JPS5378739A (en) * 1976-12-23 1978-07-12 Toshiba Corp Memory control unit
JPS5380292A (en) * 1976-12-24 1978-07-15 Kamiuchi Electric Works Method and apparatus for detection of rain and shine

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4830332A (en) * 1971-08-18 1973-04-21
JPS5311334A (en) * 1976-07-19 1978-02-01 Toshiba Corp Microwave heater
JPS5378739A (en) * 1976-12-23 1978-07-12 Toshiba Corp Memory control unit
JPS5380292A (en) * 1976-12-24 1978-07-15 Kamiuchi Electric Works Method and apparatus for detection of rain and shine

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