JPS553018A - Computer device - Google Patents

Computer device

Info

Publication number
JPS553018A
JPS553018A JP7458178A JP7458178A JPS553018A JP S553018 A JPS553018 A JP S553018A JP 7458178 A JP7458178 A JP 7458178A JP 7458178 A JP7458178 A JP 7458178A JP S553018 A JPS553018 A JP S553018A
Authority
JP
Japan
Prior art keywords
data
unit
transfer
sent
check
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7458178A
Other languages
Japanese (ja)
Inventor
Matsuo Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP7458178A priority Critical patent/JPS553018A/en
Publication of JPS553018A publication Critical patent/JPS553018A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)

Abstract

PURPOSE: To enhance the reliability of the composite calculation system by giving the periodical checking to the data transfer between the arithmetic devices connected to the common bus in order to monitor whether the transfer is normal or not.
CONSTITUTION: Unit check codes 21W23 are sent to common bus 11 periodically from arithmetic unit 12A and then received at arithmetic unit 12B. And immediately unit answer data 31W34 are sent to bus 11. When receiving the answer data by the next sending period after sending the unit check code, data transfer check function 15A checks the agreement between code 33 and 32. And when the agreement is obtained, the normal transfer is decided for the transfer of unit 12B decided by number 34 to then memorize the fact of reception. The preceding reception fact is checked in the next sending period, and the next check data is sent only when the reception is detected. And the next check data is sent after the warning is given to the fact of nonreception. In such way, the arithmetic unit is monitored, thus ensuring dealing of a large amount of the data with a high speed as well as high reliability.
COPYRIGHT: (C)1980,JPO&Japio
JP7458178A 1978-06-20 1978-06-20 Computer device Pending JPS553018A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7458178A JPS553018A (en) 1978-06-20 1978-06-20 Computer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7458178A JPS553018A (en) 1978-06-20 1978-06-20 Computer device

Publications (1)

Publication Number Publication Date
JPS553018A true JPS553018A (en) 1980-01-10

Family

ID=13551267

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7458178A Pending JPS553018A (en) 1978-06-20 1978-06-20 Computer device

Country Status (1)

Country Link
JP (1) JPS553018A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0227442A (en) * 1988-07-15 1990-01-30 Nec Corp Fault detecting system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0227442A (en) * 1988-07-15 1990-01-30 Nec Corp Fault detecting system

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