JPS5530288A - Bit-synchronous control system - Google Patents

Bit-synchronous control system

Info

Publication number
JPS5530288A
JPS5530288A JP10430678A JP10430678A JPS5530288A JP S5530288 A JPS5530288 A JP S5530288A JP 10430678 A JP10430678 A JP 10430678A JP 10430678 A JP10430678 A JP 10430678A JP S5530288 A JPS5530288 A JP S5530288A
Authority
JP
Japan
Prior art keywords
pulse
bit
synchronizing code
width
sampling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10430678A
Other languages
Japanese (ja)
Inventor
Katsuji Murata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kokusai Denki Electric Inc
Original Assignee
Hitachi Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP10430678A priority Critical patent/JPS5530288A/en
Publication of JPS5530288A publication Critical patent/JPS5530288A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0332—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with an integrator-detector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To simplify the constitution of a communication controller by controlling the generation of sampling pulses for data extraction by a microcomputer. CONSTITUTION:When received bit-synchronizing code BD is ''1'', sampling pulse generating circuit 2 outputs sampling pulse SP with a phase equivalent to bit pulse width t/2 to 1st synchronizing code BD1. Counter 6b counts timing pulses and comparator 6c makes a comparison between the count value and preset numerals indicating the upper limit and lower limit of the allowable pulse width. when the count value is between the upper and lower limints, latch 10a is set to operate the 2nd pulse-width detection circuit 7 and further, when the 2nd synchronizing code BD2 is also of the allowable pulse width, latch 10c is set. Once lathces 10a, 10b and 10c are all set, the pulse-width detection operation stops afterward. In this way, the digital control of bit synchronization can be performed.
JP10430678A 1978-08-26 1978-08-26 Bit-synchronous control system Pending JPS5530288A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10430678A JPS5530288A (en) 1978-08-26 1978-08-26 Bit-synchronous control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10430678A JPS5530288A (en) 1978-08-26 1978-08-26 Bit-synchronous control system

Publications (1)

Publication Number Publication Date
JPS5530288A true JPS5530288A (en) 1980-03-04

Family

ID=14377229

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10430678A Pending JPS5530288A (en) 1978-08-26 1978-08-26 Bit-synchronous control system

Country Status (1)

Country Link
JP (1) JPS5530288A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58190150A (en) * 1982-04-30 1983-11-07 Nec Home Electronics Ltd Clock pulse generating circuit
JPS58190148A (en) * 1982-04-30 1983-11-07 Nec Home Electronics Ltd Clock pulse generating circuit
JPH01117528A (en) * 1987-10-30 1989-05-10 Clarion Co Ltd Spread spectrum receiver

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5434707A (en) * 1977-08-24 1979-03-14 Omron Tateisi Electronics Co Data communication method and system thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5434707A (en) * 1977-08-24 1979-03-14 Omron Tateisi Electronics Co Data communication method and system thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58190150A (en) * 1982-04-30 1983-11-07 Nec Home Electronics Ltd Clock pulse generating circuit
JPS58190148A (en) * 1982-04-30 1983-11-07 Nec Home Electronics Ltd Clock pulse generating circuit
JPH01117528A (en) * 1987-10-30 1989-05-10 Clarion Co Ltd Spread spectrum receiver

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