JPS5532098U - - Google Patents
Info
- Publication number
- JPS5532098U JPS5532098U JP1979093842U JP9384279U JPS5532098U JP S5532098 U JPS5532098 U JP S5532098U JP 1979093842 U JP1979093842 U JP 1979093842U JP 9384279 U JP9384279 U JP 9384279U JP S5532098 U JPS5532098 U JP S5532098U
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07521—Aligning
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1979093842U JPS5814607Y2 (ja) | 1979-07-06 | 1979-07-06 | 半導体装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1979093842U JPS5814607Y2 (ja) | 1979-07-06 | 1979-07-06 | 半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5532098U true JPS5532098U (ja) | 1980-03-01 |
| JPS5814607Y2 JPS5814607Y2 (ja) | 1983-03-23 |
Family
ID=29025314
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1979093842U Expired JPS5814607Y2 (ja) | 1979-07-06 | 1979-07-06 | 半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5814607Y2 (ja) |
-
1979
- 1979-07-06 JP JP1979093842U patent/JPS5814607Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5814607Y2 (ja) | 1983-03-23 |