JPS5534737A - Key input read system - Google Patents

Key input read system

Info

Publication number
JPS5534737A
JPS5534737A JP10737578A JP10737578A JPS5534737A JP S5534737 A JPS5534737 A JP S5534737A JP 10737578 A JP10737578 A JP 10737578A JP 10737578 A JP10737578 A JP 10737578A JP S5534737 A JPS5534737 A JP S5534737A
Authority
JP
Japan
Prior art keywords
cpu
encoder
level
key
lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10737578A
Other languages
Japanese (ja)
Inventor
Keiichi Horitani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Tec Corp
Original Assignee
Tokyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electric Co Ltd filed Critical Tokyo Electric Co Ltd
Priority to JP10737578A priority Critical patent/JPS5534737A/en
Publication of JPS5534737A publication Critical patent/JPS5534737A/en
Pending legal-status Critical Current

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  • Input From Keyboards Or The Like (AREA)

Abstract

PURPOSE: To read an key input in a simple circuit constitution by providing a parallel input shift register and a priority encoder in a key matrix circuit.
CONSTITUTION: Parallel input shift register 2 and priority encoder 3 are connected to the output end of longitudinal lines and the output end of lateral lines of key matrix circuit 1, where longitudinal lines 1A1 to 1An, lateral lines 1B1 to 1Bn and keys K at thier intersections are arranged, respectively. When key K is operated, interrupt signal 1N is supplied from encoder 3 to CPU 4, and CPU 4 controls register 2 so that one of signals outputted from register to longitudinal lines may be low-level and others may be high-level. CPU 4 changes successively the output position of a signal which becomes low-level, and checks the output of encoder 3.
COPYRIGHT: (C)1980,JPO&Japio
JP10737578A 1978-09-01 1978-09-01 Key input read system Pending JPS5534737A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10737578A JPS5534737A (en) 1978-09-01 1978-09-01 Key input read system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10737578A JPS5534737A (en) 1978-09-01 1978-09-01 Key input read system

Publications (1)

Publication Number Publication Date
JPS5534737A true JPS5534737A (en) 1980-03-11

Family

ID=14457502

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10737578A Pending JPS5534737A (en) 1978-09-01 1978-09-01 Key input read system

Country Status (1)

Country Link
JP (1) JPS5534737A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58211238A (en) * 1982-06-02 1983-12-08 Fujitsu Ltd Key input device
JPS6026521A (en) * 1983-07-22 1985-02-09 Ube Ind Ltd Method of piling steel piece and equipment therefor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58211238A (en) * 1982-06-02 1983-12-08 Fujitsu Ltd Key input device
JPS6026521A (en) * 1983-07-22 1985-02-09 Ube Ind Ltd Method of piling steel piece and equipment therefor

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