JPS5537657A - Address extension system - Google Patents

Address extension system

Info

Publication number
JPS5537657A
JPS5537657A JP11051078A JP11051078A JPS5537657A JP S5537657 A JPS5537657 A JP S5537657A JP 11051078 A JP11051078 A JP 11051078A JP 11051078 A JP11051078 A JP 11051078A JP S5537657 A JPS5537657 A JP S5537657A
Authority
JP
Japan
Prior art keywords
block
stored
jump
subroutine
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11051078A
Other languages
Japanese (ja)
Inventor
Hitoshi Shirai
Yoshikazu Tanaka
Yoshiharu Kamio
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11051078A priority Critical patent/JPS5537657A/en
Publication of JPS5537657A publication Critical patent/JPS5537657A/en
Pending legal-status Critical Current

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  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE: To make a subroutine jump among all blocks possible by providing a register stored with memory area block assignment information and another register stored with jump-destination memory area assignment information.
CONSTITUTION: To make a jump to subroutine A stored in block MBn in the execution of a program stored in block MB0, back stack area BS, a register stored with jump-destination block assignment information, is stored with block MBn assignment information (n). Next, access to a jump instruction in block MB0 is attained by address information to be sent, thereby executing a jump to subroutine A. During this period, information (n) is written via selector SEL1 into block register BREG stored with memory area block assignment information. After the execution of subroutine A ends, a return instruction transfers and stores information, assigning original block MB0, stored in area BS in register BREG through SEL2.
COPYRIGHT: (C)1980,JPO&Japio
JP11051078A 1978-09-08 1978-09-08 Address extension system Pending JPS5537657A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11051078A JPS5537657A (en) 1978-09-08 1978-09-08 Address extension system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11051078A JPS5537657A (en) 1978-09-08 1978-09-08 Address extension system

Publications (1)

Publication Number Publication Date
JPS5537657A true JPS5537657A (en) 1980-03-15

Family

ID=14537604

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11051078A Pending JPS5537657A (en) 1978-09-08 1978-09-08 Address extension system

Country Status (1)

Country Link
JP (1) JPS5537657A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58123142A (en) * 1982-01-19 1983-07-22 Nec Corp Information processor
JPS59136850A (en) * 1983-01-26 1984-08-06 Hitachi Ltd Microprogram memory selection control method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58123142A (en) * 1982-01-19 1983-07-22 Nec Corp Information processor
JPS59136850A (en) * 1983-01-26 1984-08-06 Hitachi Ltd Microprogram memory selection control method

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