JPS5539910A - Integrating comparing system for digital differential analyzer - Google Patents

Integrating comparing system for digital differential analyzer

Info

Publication number
JPS5539910A
JPS5539910A JP10848978A JP10848978A JPS5539910A JP S5539910 A JPS5539910 A JP S5539910A JP 10848978 A JP10848978 A JP 10848978A JP 10848978 A JP10848978 A JP 10848978A JP S5539910 A JPS5539910 A JP S5539910A
Authority
JP
Japan
Prior art keywords
output
value
adder
register
result
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10848978A
Other languages
Japanese (ja)
Inventor
Saburo Sogo
Akio Jo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kokusai Denki Electric Inc
Original Assignee
Hitachi Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP10848978A priority Critical patent/JPS5539910A/en
Publication of JPS5539910A publication Critical patent/JPS5539910A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To set a predetermined value at a register in case the result of computing to a some value is only required, compare it with the computing result, and stop the operation when they coincide with each other.
CONSTITUTION: As input of the adder AD2, the output of the multiplier MUL and the content of the register RY are given. Since the preceding output result of the adder AD2 is stored in the register RY, in the adder AD2, the sum of the content of the register RY Yi-1 and the increment ΔYi from the multiplier MUL is added to the product of the scaling value of SΣΔYi and the operation result is obtained by the division quadrature method. To the output of the adder AD2, the judging circuit JD for judging and detecting the particular value produced in a output value at the output side is added, and the detecting output thereof maintains the output value of the hold circuit HD to stop the operation of the address counter CUA and enforcedly stop the operation of the arithmetic circuit OP.
COPYRIGHT: (C)1980,JPO&Japio
JP10848978A 1978-09-06 1978-09-06 Integrating comparing system for digital differential analyzer Pending JPS5539910A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10848978A JPS5539910A (en) 1978-09-06 1978-09-06 Integrating comparing system for digital differential analyzer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10848978A JPS5539910A (en) 1978-09-06 1978-09-06 Integrating comparing system for digital differential analyzer

Publications (1)

Publication Number Publication Date
JPS5539910A true JPS5539910A (en) 1980-03-21

Family

ID=14486052

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10848978A Pending JPS5539910A (en) 1978-09-06 1978-09-06 Integrating comparing system for digital differential analyzer

Country Status (1)

Country Link
JP (1) JPS5539910A (en)

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