JPS554132A - Schmitt circuit - Google Patents

Schmitt circuit

Info

Publication number
JPS554132A
JPS554132A JP7687378A JP7687378A JPS554132A JP S554132 A JPS554132 A JP S554132A JP 7687378 A JP7687378 A JP 7687378A JP 7687378 A JP7687378 A JP 7687378A JP S554132 A JPS554132 A JP S554132A
Authority
JP
Japan
Prior art keywords
input state
fetq3
fetq2
drain
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7687378A
Other languages
Japanese (ja)
Inventor
Masaharu Sato
Takeshi Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP7687378A priority Critical patent/JPS554132A/en
Publication of JPS554132A publication Critical patent/JPS554132A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger

Landscapes

  • Manipulation Of Pulses (AREA)
  • Pulse Circuits (AREA)

Abstract

PURPOSE:To make it possible to extract a constant and low current regardless of an input state by using a switching element which turns ON-OFF depending upon the input state, as a trigger-level setting resistance. CONSTITUTION:The drain of FETQ1 supplied at its gate with an input signal is connected power supply VDD via resistance R3 and also to the gate of FETQ2 and the input terminal of inverter 4, the drain of FETQ2 is also connected to power supply VDD, and the source of FETQ2 is grounded via resistances R4 and R6. Here, the drain of FETQ3 with its source grounded is connected to the source of FETQ1 and the terminal at the opposite side to the grounded terminal of resistance R6 and the output of inverter 4 is led to the gate of FETQ3. Consequently, the switching element composed of FETQ3 turning ON-OFF depending upon the input state is used as a trigger-level setting resistance to make it possible to extract a constant and low current regardless of the input state.
JP7687378A 1978-06-23 1978-06-23 Schmitt circuit Pending JPS554132A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7687378A JPS554132A (en) 1978-06-23 1978-06-23 Schmitt circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7687378A JPS554132A (en) 1978-06-23 1978-06-23 Schmitt circuit

Publications (1)

Publication Number Publication Date
JPS554132A true JPS554132A (en) 1980-01-12

Family

ID=13617747

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7687378A Pending JPS554132A (en) 1978-06-23 1978-06-23 Schmitt circuit

Country Status (1)

Country Link
JP (1) JPS554132A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49148453U (en) * 1973-04-19 1974-12-21
JPS63174420A (en) * 1987-01-13 1988-07-18 Nec Corp Hysteresis circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4829751B1 (en) * 1970-11-26 1973-09-13

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4829751B1 (en) * 1970-11-26 1973-09-13

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49148453U (en) * 1973-04-19 1974-12-21
JPS63174420A (en) * 1987-01-13 1988-07-18 Nec Corp Hysteresis circuit

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