JPS5542373A - Clock unit of pcm decoder - Google Patents

Clock unit of pcm decoder

Info

Publication number
JPS5542373A
JPS5542373A JP11611578A JP11611578A JPS5542373A JP S5542373 A JPS5542373 A JP S5542373A JP 11611578 A JP11611578 A JP 11611578A JP 11611578 A JP11611578 A JP 11611578A JP S5542373 A JPS5542373 A JP S5542373A
Authority
JP
Japan
Prior art keywords
signal
generator
regenerative
synchronizing
synchronous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11611578A
Other languages
Japanese (ja)
Inventor
Tetsuo Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TRIO KENWOOD CORP
Kenwood KK
Original Assignee
TRIO KENWOOD CORP
Kenwood KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TRIO KENWOOD CORP, Kenwood KK filed Critical TRIO KENWOOD CORP
Priority to JP11611578A priority Critical patent/JPS5542373A/en
Publication of JPS5542373A publication Critical patent/JPS5542373A/en
Pending legal-status Critical Current

Links

Landscapes

  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

PURPOSE: To prevent level variation of a reproduced signal of PCM decoding and deterioration in tone quality by providing an asynchronous generator and then by synchronizing a recording medium driver with it.
CONSTITUTION: As a regenerative synchronous signal, regenerative synchronous signal generator 7, for example, using crystal vibrator 6 is used and a synchronizing signal from a synchronising signal separator 2 is not synchronized to obtain a synchronous generator. Then, a phase comparison between the above-mentioned signals is made by phase comparator 8 and this output is fed as a control signal back to VTR 1 and then applied to the speed control part of a recording medium driver provided outside of VTR, i.e. an adjustment circuit for a regeneration speed, thereby attaining synchronization with the asynchronous generator. In tihs way, variation and deterioration in tone quality of the regenerative signal due to the jitters of the synchronizing signal in PCM decoding can be prevented.
COPYRIGHT: (C)1980,JPO&Japio
JP11611578A 1978-09-20 1978-09-20 Clock unit of pcm decoder Pending JPS5542373A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11611578A JPS5542373A (en) 1978-09-20 1978-09-20 Clock unit of pcm decoder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11611578A JPS5542373A (en) 1978-09-20 1978-09-20 Clock unit of pcm decoder

Publications (1)

Publication Number Publication Date
JPS5542373A true JPS5542373A (en) 1980-03-25

Family

ID=14679054

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11611578A Pending JPS5542373A (en) 1978-09-20 1978-09-20 Clock unit of pcm decoder

Country Status (1)

Country Link
JP (1) JPS5542373A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4842917U (en) * 1971-09-25 1973-06-02

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4842917U (en) * 1971-09-25 1973-06-02

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