JPS5543603A - Electronic computer - Google Patents

Electronic computer

Info

Publication number
JPS5543603A
JPS5543603A JP11508178A JP11508178A JPS5543603A JP S5543603 A JPS5543603 A JP S5543603A JP 11508178 A JP11508178 A JP 11508178A JP 11508178 A JP11508178 A JP 11508178A JP S5543603 A JPS5543603 A JP S5543603A
Authority
JP
Japan
Prior art keywords
cpu
lsi
operation speed
information
registers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11508178A
Other languages
Japanese (ja)
Inventor
Tsuneo Kinoshita
Kazuyuki Sato
Keikichi Tamaru
Tai Sato
Isamu Yamazaki
Misao Miyata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11508178A priority Critical patent/JPS5543603A/en
Publication of JPS5543603A publication Critical patent/JPS5543603A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To realize a compact design for the computer as well as to increase the operation speed of the CPU by unifying the sequence control unit and the arithmetic unit through the LSI formation.
CONSTITUTION: With the LSI formation of the CPU, the operation speed can be increased for the CPU. However, the acceleration is limited by the size of the LSI package and the number of pins. In this connection, the data access is carried out via information converter 500 between the memory and CPU. The 32-bit width information read out from main memory device 100 are registered into registers 501W504 with every 8 bits, and the information registered into the registers are transferred to the CPU with every 16 bits. The writing of the information into device 100 is performed in the similar way, thus increasing the operation speed for the CPU. At the same time, the number of pins of the LSI can be reduced greatly through the 32/16-bit conversion.
COPYRIGHT: (C)1980,JPO&Japio
JP11508178A 1978-09-21 1978-09-21 Electronic computer Pending JPS5543603A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11508178A JPS5543603A (en) 1978-09-21 1978-09-21 Electronic computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11508178A JPS5543603A (en) 1978-09-21 1978-09-21 Electronic computer

Publications (1)

Publication Number Publication Date
JPS5543603A true JPS5543603A (en) 1980-03-27

Family

ID=14653706

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11508178A Pending JPS5543603A (en) 1978-09-21 1978-09-21 Electronic computer

Country Status (1)

Country Link
JP (1) JPS5543603A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6453299A (en) * 1987-08-24 1989-03-01 Toshiba Corp Data output system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS503284A (en) * 1973-05-12 1975-01-14
JPS5119949A (en) * 1974-08-09 1976-02-17 Fujitsu Ltd DEETASHORISOCHI

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS503284A (en) * 1973-05-12 1975-01-14
JPS5119949A (en) * 1974-08-09 1976-02-17 Fujitsu Ltd DEETASHORISOCHI

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6453299A (en) * 1987-08-24 1989-03-01 Toshiba Corp Data output system

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