JPS5545208A - Phase detection circuit - Google Patents

Phase detection circuit

Info

Publication number
JPS5545208A
JPS5545208A JP11783778A JP11783778A JPS5545208A JP S5545208 A JPS5545208 A JP S5545208A JP 11783778 A JP11783778 A JP 11783778A JP 11783778 A JP11783778 A JP 11783778A JP S5545208 A JPS5545208 A JP S5545208A
Authority
JP
Japan
Prior art keywords
sampling
pulses
circuit
timing
generation circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11783778A
Other languages
Japanese (ja)
Inventor
Yoshimitsu Okano
Tateo Kamiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11783778A priority Critical patent/JPS5545208A/en
Publication of JPS5545208A publication Critical patent/JPS5545208A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/22—Demodulator circuits; Receiver circuits
    • H04L27/227—Demodulator circuits; Receiver circuits using coherent demodulation
    • H04L27/2275—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses the received modulated signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To obtain a detection circut where a low-pass filter, etc., are needless and receiving signals can be detected, by sampling receiving signals by timing pulses and sampling pulses which are generated by using a reference carrier and are controlled on the time base. CONSTITUTION:A phase modulation wave is not only given to sampling circuit 14 as a receiving signal but also supplied to timing generation circuit 15 and reference carrier circuit 16. Timing generation circuit 15 generates a timing pulse synchronized with the receiving signal at every one time slot and sends it to sampling pulse generation circuit 17. Meanwhile, reference wave generation circuit 16 supplies the reference carrier to sampling position control circuit 18 correspondingly to the phase modulation wave. Here, timing pulses and reference sampling pulses are used to sample pulses 20 which have the position controlled on the time base. Receiving pulses 20, sampling circuit 14 samples receiving signals and reads the sample result as it is. As a result, the precision of the sample result is improved, and a low-pass filter, etc., can be made needless.
JP11783778A 1978-09-27 1978-09-27 Phase detection circuit Pending JPS5545208A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11783778A JPS5545208A (en) 1978-09-27 1978-09-27 Phase detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11783778A JPS5545208A (en) 1978-09-27 1978-09-27 Phase detection circuit

Publications (1)

Publication Number Publication Date
JPS5545208A true JPS5545208A (en) 1980-03-29

Family

ID=14721473

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11783778A Pending JPS5545208A (en) 1978-09-27 1978-09-27 Phase detection circuit

Country Status (1)

Country Link
JP (1) JPS5545208A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012109647A (en) * 2010-11-15 2012-06-07 Renesas Electronics Corp Semiconductor integrated circuit and method of operating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012109647A (en) * 2010-11-15 2012-06-07 Renesas Electronics Corp Semiconductor integrated circuit and method of operating the same

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