JPS5552152A - Control system for program address - Google Patents

Control system for program address

Info

Publication number
JPS5552152A
JPS5552152A JP12512078A JP12512078A JPS5552152A JP S5552152 A JPS5552152 A JP S5552152A JP 12512078 A JP12512078 A JP 12512078A JP 12512078 A JP12512078 A JP 12512078A JP S5552152 A JPS5552152 A JP S5552152A
Authority
JP
Japan
Prior art keywords
address
stacker
level
shunted
transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12512078A
Other languages
Japanese (ja)
Inventor
Kazunobu Mimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12512078A priority Critical patent/JPS5552152A/en
Publication of JPS5552152A publication Critical patent/JPS5552152A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To simplify the control without requiring the recognition of processing level at transfer, by shunting and restoration with the address stacker of address designation in continuity for the program address at transfer between processing levels of various types.
CONSTITUTION: During the running at a program running level E, when the request 10 of transfer to the higher level D is taken place, the stack address counter 2 is added by +1, and the address E of the level E scheduled to processed next is shunted to the stacker I of the address stacker 1 sequentially being represented in the counter 2. Further, if the request to higher level is present, it is shunted to the address stacker 1 sequentially. Further, if a processing is finished, the address shunted at the final part of the address stacker 1 is picked with the address selection circuit 5, and the control is transferred to the level corresponded.
COPYRIGHT: (C)1980,JPO&Japio
JP12512078A 1978-10-13 1978-10-13 Control system for program address Pending JPS5552152A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12512078A JPS5552152A (en) 1978-10-13 1978-10-13 Control system for program address

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12512078A JPS5552152A (en) 1978-10-13 1978-10-13 Control system for program address

Publications (1)

Publication Number Publication Date
JPS5552152A true JPS5552152A (en) 1980-04-16

Family

ID=14902332

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12512078A Pending JPS5552152A (en) 1978-10-13 1978-10-13 Control system for program address

Country Status (1)

Country Link
JP (1) JPS5552152A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS575156A (en) * 1980-05-07 1982-01-11 Fairchild Camera Instr Co Interruptible microprogram sequence device
JPS59111542A (en) * 1982-12-03 1984-06-27 ハネイウエル・インフオメ−シヨン・システムス・インコ−ポレ−テツド Program counter stack method and nested subroutine and instruction apparatus
JPH01102653A (en) * 1987-10-14 1989-04-20 Nec Corp Microprogram control system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5023948A (en) * 1973-07-02 1975-03-14
JPS518829A (en) * 1974-07-09 1976-01-24 Hitachi Ltd
JPS51150938A (en) * 1975-06-19 1976-12-24 Toyoda Mach Works Ltd Interrupt handling unit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5023948A (en) * 1973-07-02 1975-03-14
JPS518829A (en) * 1974-07-09 1976-01-24 Hitachi Ltd
JPS51150938A (en) * 1975-06-19 1976-12-24 Toyoda Mach Works Ltd Interrupt handling unit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS575156A (en) * 1980-05-07 1982-01-11 Fairchild Camera Instr Co Interruptible microprogram sequence device
JPS59111542A (en) * 1982-12-03 1984-06-27 ハネイウエル・インフオメ−シヨン・システムス・インコ−ポレ−テツド Program counter stack method and nested subroutine and instruction apparatus
JPH01102653A (en) * 1987-10-14 1989-04-20 Nec Corp Microprogram control system

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