JPS5559563A - Error detector - Google Patents

Error detector

Info

Publication number
JPS5559563A
JPS5559563A JP13341578A JP13341578A JPS5559563A JP S5559563 A JPS5559563 A JP S5559563A JP 13341578 A JP13341578 A JP 13341578A JP 13341578 A JP13341578 A JP 13341578A JP S5559563 A JPS5559563 A JP S5559563A
Authority
JP
Japan
Prior art keywords
parity
parity bit
register
bit
adders
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13341578A
Other languages
Japanese (ja)
Other versions
JPS6136258B2 (en
Inventor
Kozo Yamano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13341578A priority Critical patent/JPS5559563A/en
Publication of JPS5559563A publication Critical patent/JPS5559563A/en
Publication of JPS6136258B2 publication Critical patent/JPS6136258B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Hardware Redundancy (AREA)

Abstract

PURPOSE: To accelerate the machine cycle and thus to enhance the system performance by detecting the parity error based on the couple of the arithmetic result and the parity bit.
CONSTITUTION: The data bit output of 1st and 2nd registers 1 and 2 which store operands 1 and 2 added with parity bit P are applied to 1st and 2nd adders 3 and 4 but with no addition of the parity bit. In this connection, the reghtfulness of the input data is checked at parity check circuit 5. The addition result is given to holding register 6 and parity generation register 7. When the addition result is stored in register 6, the parity bit is set forcedly to zero in order to secure the check of the rightfulness for both 1st and 2nd adders 3 and 4.
COPYRIGHT: (C)1980,JPO&Japio
JP13341578A 1978-10-30 1978-10-30 Error detector Granted JPS5559563A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13341578A JPS5559563A (en) 1978-10-30 1978-10-30 Error detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13341578A JPS5559563A (en) 1978-10-30 1978-10-30 Error detector

Publications (2)

Publication Number Publication Date
JPS5559563A true JPS5559563A (en) 1980-05-06
JPS6136258B2 JPS6136258B2 (en) 1986-08-18

Family

ID=15104228

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13341578A Granted JPS5559563A (en) 1978-10-30 1978-10-30 Error detector

Country Status (1)

Country Link
JP (1) JPS5559563A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5494851A (en) * 1978-01-10 1979-07-26 Nec Corp Data processor
JPS5916303A (en) * 1982-07-19 1984-01-27 松下冷機株式会社 Method of producing semiconductor porcelain material

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5494851A (en) * 1978-01-10 1979-07-26 Nec Corp Data processor
JPS5916303A (en) * 1982-07-19 1984-01-27 松下冷機株式会社 Method of producing semiconductor porcelain material

Also Published As

Publication number Publication date
JPS6136258B2 (en) 1986-08-18

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