JPS5564614A - Code converting circuit - Google Patents

Code converting circuit

Info

Publication number
JPS5564614A
JPS5564614A JP13695778A JP13695778A JPS5564614A JP S5564614 A JPS5564614 A JP S5564614A JP 13695778 A JP13695778 A JP 13695778A JP 13695778 A JP13695778 A JP 13695778A JP S5564614 A JPS5564614 A JP S5564614A
Authority
JP
Japan
Prior art keywords
carry
data
buffer
circuit
generating circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13695778A
Other languages
Japanese (ja)
Other versions
JPS6231427B2 (en
Inventor
Yoshiaki Sugiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13695778A priority Critical patent/JPS5564614A/en
Publication of JPS5564614A publication Critical patent/JPS5564614A/en
Publication of JPS6231427B2 publication Critical patent/JPS6231427B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Dc Digital Transmission (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

PURPOSE: To reduce the propagation time of signals with logic circuits reduced in number by providing an arithmetic method of performing prescribed arithmetic on the basis of split-unit data from a data storage method and carry signal from shift register corresponding to this data.
CONSTITUTION: In a code converter circuit which performs ZM (Zero Modilation) belonging to GCR (Group Cord Recording), P(A) generating circuit 3 consists of all-"1" detection circuit 3a detecting the all-"1" mode of data transmitted from data register 1 through bus 13ab, carry generating circuit 3b which inhibits the propagation of a P(A) carry shown by formula I, generating circuit 3d which generates P(A) for a certain group by data sent from register 1 through bus 13d and a carry from buffer 3c, carry buffer 3c stored with carry bits, buffer circuit 3e stored with P(A) generated as mentioned above, counter 3f counting groups for generating P(A) carries, and decoder 3g which generate a gate signal for the carry buffer. Consequently, logic circuits can be reduced in number to shorten the propagation time of signals.
COPYRIGHT: (C)1980,JPO&Japio
JP13695778A 1978-11-07 1978-11-07 Code converting circuit Granted JPS5564614A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13695778A JPS5564614A (en) 1978-11-07 1978-11-07 Code converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13695778A JPS5564614A (en) 1978-11-07 1978-11-07 Code converting circuit

Publications (2)

Publication Number Publication Date
JPS5564614A true JPS5564614A (en) 1980-05-15
JPS6231427B2 JPS6231427B2 (en) 1987-07-08

Family

ID=15187449

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13695778A Granted JPS5564614A (en) 1978-11-07 1978-11-07 Code converting circuit

Country Status (1)

Country Link
JP (1) JPS5564614A (en)

Also Published As

Publication number Publication date
JPS6231427B2 (en) 1987-07-08

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