JPS5565164A - Decoder check circuit - Google Patents

Decoder check circuit

Info

Publication number
JPS5565164A
JPS5565164A JP13778978A JP13778978A JPS5565164A JP S5565164 A JPS5565164 A JP S5565164A JP 13778978 A JP13778978 A JP 13778978A JP 13778978 A JP13778978 A JP 13778978A JP S5565164 A JPS5565164 A JP S5565164A
Authority
JP
Japan
Prior art keywords
input
decoder
output
pattern
failure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13778978A
Other languages
Japanese (ja)
Other versions
JPS5855531B2 (en
Inventor
Shinichi Ito
Takashi Nara
Yuji Tokunaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53137789A priority Critical patent/JPS5855531B2/en
Publication of JPS5565164A publication Critical patent/JPS5565164A/en
Publication of JPS5855531B2 publication Critical patent/JPS5855531B2/en
Expired legal-status Critical Current

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Abstract

PURPOSE: To reduce the price by detecting the reduction failure of input and output of decoder with less number of logic elements.
CONSTITUTION: In the input of the checked decoder 11, if the failure in reduction is produced, when the change of one period from (000) to (111) for the input pattern is taken place, it is surely present that the output state of the decoder 11 is not changed refardless of the change in the input pattern. For example, the input bo is reduced to "1", the state of output is not entirely changed even if the pattern of (b2 b1 bo) is changed from (000) to (001), and in either case, the output D1 remains "1". In this case, the output of the check decoder 12 follows the change in the input pattern. Since c1 is "1" after Co is "1", the input state of the 1/N check circuit is all "0" to the input pattern (001) enabling to detect the presence of failure in the decoder.
COPYRIGHT: (C)1980,JPO&Japio
JP53137789A 1978-11-10 1978-11-10 Decoder check circuit Expired JPS5855531B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53137789A JPS5855531B2 (en) 1978-11-10 1978-11-10 Decoder check circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53137789A JPS5855531B2 (en) 1978-11-10 1978-11-10 Decoder check circuit

Publications (2)

Publication Number Publication Date
JPS5565164A true JPS5565164A (en) 1980-05-16
JPS5855531B2 JPS5855531B2 (en) 1983-12-10

Family

ID=15206876

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53137789A Expired JPS5855531B2 (en) 1978-11-10 1978-11-10 Decoder check circuit

Country Status (1)

Country Link
JP (1) JPS5855531B2 (en)

Also Published As

Publication number Publication date
JPS5855531B2 (en) 1983-12-10

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