JPS5566012A - Input signal circuit - Google Patents

Input signal circuit

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Publication number
JPS5566012A
JPS5566012A JP13815478A JP13815478A JPS5566012A JP S5566012 A JPS5566012 A JP S5566012A JP 13815478 A JP13815478 A JP 13815478A JP 13815478 A JP13815478 A JP 13815478A JP S5566012 A JPS5566012 A JP S5566012A
Authority
JP
Japan
Prior art keywords
signal
circuit
input signal
make
den
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13815478A
Other languages
Japanese (ja)
Inventor
Tokutaro Shinpo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP13815478A priority Critical patent/JPS5566012A/en
Publication of JPS5566012A publication Critical patent/JPS5566012A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To make it possible to reduce power loss, make a circuit small-size and make a signal voltage range wide by inserting a switching circuit, which is closed only when input signal fetch control signals are applied, in series to a loop circuit.
CONSTITUTION: Switching circuit 12 consisting of buffer amplifier BA, resistor RS10, photo coupler PC10 and transistor Tr is provided in series for a loop circuit including resistor RS7 of input part I7 of each signal path and signal source VX8 for the resistor group. Input signal fetch control signal DEN is applied to not only buffer gate BGn but also circuit 12 to close circuit 12 and flows a current through RS7 only when signal DEN is applied, thus transmitting signals to data bus DB7. The width of signal DEN is set to a time required for normal input signal fetch, and this time is approximately several μ seconds at longest considering the normal operation of these circuits, so that power loss can be very small.
COPYRIGHT: (C)1980,JPO&Japio
JP13815478A 1978-11-09 1978-11-09 Input signal circuit Pending JPS5566012A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13815478A JPS5566012A (en) 1978-11-09 1978-11-09 Input signal circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13815478A JPS5566012A (en) 1978-11-09 1978-11-09 Input signal circuit

Publications (1)

Publication Number Publication Date
JPS5566012A true JPS5566012A (en) 1980-05-19

Family

ID=15215274

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13815478A Pending JPS5566012A (en) 1978-11-09 1978-11-09 Input signal circuit

Country Status (1)

Country Link
JP (1) JPS5566012A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS578827A (en) * 1980-06-19 1982-01-18 Mitsubishi Electric Corp Input controller
JPS5741730A (en) * 1980-08-26 1982-03-09 Mitsubishi Electric Corp Digital input circuit
US6543353B1 (en) 1998-06-18 2003-04-08 Koenig & Bauer Aktiengesellschaft Method for monitoring a strip of fabric

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS578827A (en) * 1980-06-19 1982-01-18 Mitsubishi Electric Corp Input controller
JPS5741730A (en) * 1980-08-26 1982-03-09 Mitsubishi Electric Corp Digital input circuit
US6543353B1 (en) 1998-06-18 2003-04-08 Koenig & Bauer Aktiengesellschaft Method for monitoring a strip of fabric

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