JPS556622A - Microprogram sequence control circuuit - Google Patents

Microprogram sequence control circuuit

Info

Publication number
JPS556622A
JPS556622A JP7873478A JP7873478A JPS556622A JP S556622 A JPS556622 A JP S556622A JP 7873478 A JP7873478 A JP 7873478A JP 7873478 A JP7873478 A JP 7873478A JP S556622 A JPS556622 A JP S556622A
Authority
JP
Japan
Prior art keywords
address
input
adder
bits
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7873478A
Other languages
Japanese (ja)
Other versions
JPS6115456B2 (en
Inventor
Noriaki Matsumoto
Masato Maruyama
Takeshi Miyamoto
Mitsuyoshi Nagatani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Iwatsu Electric Co Ltd
NTT Inc
Original Assignee
Iwatsu Electric Co Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Iwatsu Electric Co Ltd, Nippon Telegraph and Telephone Corp filed Critical Iwatsu Electric Co Ltd
Priority to JP7873478A priority Critical patent/JPS556622A/en
Publication of JPS556622A publication Critical patent/JPS556622A/en
Publication of JPS6115456B2 publication Critical patent/JPS6115456B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To realize various addressing functions required for programming by a simple constitution, by allowing an address register to generate the next address by a relative address system or increment address system.
CONSTITUTION: Full adder 8 has the "n"-number input bits half as many as the "2n"-number address bits to be outputted and bit width 2n as wide as number 2n of output bits, and to one input of adder 8, the output of address register 3 supplied with the output of adder 8 is applied. To the other input of adder 8, data with the higher or lower bit (n) of input bits controlled by input cpntrol circuit 11 made "O" or all "O" data is applied. Consequently, the simple constitution can realize various addressing functions needed for programming, by generating the next address in register 3 by the relative address system or increment system.
COPYRIGHT: (C)1980,JPO&Japio
JP7873478A 1978-06-30 1978-06-30 Microprogram sequence control circuuit Granted JPS556622A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7873478A JPS556622A (en) 1978-06-30 1978-06-30 Microprogram sequence control circuuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7873478A JPS556622A (en) 1978-06-30 1978-06-30 Microprogram sequence control circuuit

Publications (2)

Publication Number Publication Date
JPS556622A true JPS556622A (en) 1980-01-18
JPS6115456B2 JPS6115456B2 (en) 1986-04-24

Family

ID=13670105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7873478A Granted JPS556622A (en) 1978-06-30 1978-06-30 Microprogram sequence control circuuit

Country Status (1)

Country Link
JP (1) JPS556622A (en)

Also Published As

Publication number Publication date
JPS6115456B2 (en) 1986-04-24

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