JPS55672A - Phase synchronous circuit - Google Patents

Phase synchronous circuit

Info

Publication number
JPS55672A
JPS55672A JP16113478A JP16113478A JPS55672A JP S55672 A JPS55672 A JP S55672A JP 16113478 A JP16113478 A JP 16113478A JP 16113478 A JP16113478 A JP 16113478A JP S55672 A JPS55672 A JP S55672A
Authority
JP
Japan
Prior art keywords
output
circuit
becomes
waveform
identification
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16113478A
Other languages
Japanese (ja)
Inventor
Hideo Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP16113478A priority Critical patent/JPS55672A/en
Publication of JPS55672A publication Critical patent/JPS55672A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/22—Demodulator circuits; Receiver circuits
    • H04L27/227—Demodulator circuits; Receiver circuits using coherent demodulation
    • H04L27/2271—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses only the demodulated signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To decrease the number of the circuits used with omission of the new phase comparator by using the detection demodulator for the phase comparator of the phase synchronous loop. CONSTITUTION:As for output (a) and (b) of phase comparator 2 and 3, the output of difference arithmetic circuit 4 becomes (c) and the digital output of waveform identification shaping circuit 6 becomes (d). And the output of sum arithmetic circuit 5 of output (a) and (b) becomes (e), and the digital output of waveform identification shaping circuit 7 becomes (f). Output (d) and (f) undergo the exclusive logic sum operation at logic circuit 10 to be turned to (g). On the other hand, output (a) and (b) are shaped through identification shaping circuit 8 and 9, and waveform (h) becomes (i). Then the exclusive logic sum operation is performed at logic circuit 11 to obtain waveform (j), and then the exclusive logic sum operation is given to waveform (g) and (j) at circuit 12.
JP16113478A 1978-12-28 1978-12-28 Phase synchronous circuit Pending JPS55672A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16113478A JPS55672A (en) 1978-12-28 1978-12-28 Phase synchronous circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16113478A JPS55672A (en) 1978-12-28 1978-12-28 Phase synchronous circuit

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP7661472A Division JPS539704B2 (en) 1972-07-31 1972-07-31

Publications (1)

Publication Number Publication Date
JPS55672A true JPS55672A (en) 1980-01-07

Family

ID=15729234

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16113478A Pending JPS55672A (en) 1978-12-28 1978-12-28 Phase synchronous circuit

Country Status (1)

Country Link
JP (1) JPS55672A (en)

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