JPS5567832A - Matrix key extension circuit - Google Patents

Matrix key extension circuit

Info

Publication number
JPS5567832A
JPS5567832A JP14117778A JP14117778A JPS5567832A JP S5567832 A JPS5567832 A JP S5567832A JP 14117778 A JP14117778 A JP 14117778A JP 14117778 A JP14117778 A JP 14117778A JP S5567832 A JPS5567832 A JP S5567832A
Authority
JP
Japan
Prior art keywords
key
matrix
circuit
cpu4
data bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14117778A
Other languages
Japanese (ja)
Inventor
Yasushi Imai
Zenji Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Tec Corp
Original Assignee
Tokyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electric Co Ltd filed Critical Tokyo Electric Co Ltd
Priority to JP14117778A priority Critical patent/JPS5567832A/en
Publication of JPS5567832A publication Critical patent/JPS5567832A/en
Pending legal-status Critical Current

Links

Landscapes

  • Input From Keyboards Or The Like (AREA)

Abstract

PURPOSE: To secure the increment for the unit number of the matrix keys up to a multiple of the allowed number which is can be connected to the CPU by supplying the output of the matrix key in each block to the data bus line of the CPU via the FF circuit.
CONSTITUTION: It is supposed that a certain matrix key 12b is pressed within block B through the key operation of keyboard 6. In this case, the key retrieval signal is drawn into key input terminals PK0WPK3 of CPU4 and also supplied to FF circuit 15b via gate 14b. And the output of circuit 15b is delivered to the data bus line of CPU4. Then the matrix key supplied is decided by the retrieval signal drawn into terminal PK0 or the like of CPU4 plus the signal delivered to the data bus line from circuit 15b. As a result, the unit number of matrix keys can be increased up to a multiple of the allowed number which can be connected to COU4.
COPYRIGHT: (C)1980,JPO&Japio
JP14117778A 1978-11-17 1978-11-17 Matrix key extension circuit Pending JPS5567832A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14117778A JPS5567832A (en) 1978-11-17 1978-11-17 Matrix key extension circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14117778A JPS5567832A (en) 1978-11-17 1978-11-17 Matrix key extension circuit

Publications (1)

Publication Number Publication Date
JPS5567832A true JPS5567832A (en) 1980-05-22

Family

ID=15285928

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14117778A Pending JPS5567832A (en) 1978-11-17 1978-11-17 Matrix key extension circuit

Country Status (1)

Country Link
JP (1) JPS5567832A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5953446U (en) * 1982-09-29 1984-04-07 横河電機株式会社 distributed keyboard
JPS62138237U (en) * 1986-02-20 1987-08-31
US5323153A (en) * 1990-02-14 1994-06-21 Sharp Kabushiki Kaisha Keyboard connection apparatus and keyboard input apparatus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5953446U (en) * 1982-09-29 1984-04-07 横河電機株式会社 distributed keyboard
JPS62138237U (en) * 1986-02-20 1987-08-31
US5323153A (en) * 1990-02-14 1994-06-21 Sharp Kabushiki Kaisha Keyboard connection apparatus and keyboard input apparatus

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