JPS5567853A - Logic device - Google Patents

Logic device

Info

Publication number
JPS5567853A
JPS5567853A JP14144678A JP14144678A JPS5567853A JP S5567853 A JPS5567853 A JP S5567853A JP 14144678 A JP14144678 A JP 14144678A JP 14144678 A JP14144678 A JP 14144678A JP S5567853 A JPS5567853 A JP S5567853A
Authority
JP
Japan
Prior art keywords
address
line
jump
memory
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14144678A
Other languages
Japanese (ja)
Other versions
JPS6142301B2 (en
Inventor
Katsumi Uchida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14144678A priority Critical patent/JPS5567853A/en
Publication of JPS5567853A publication Critical patent/JPS5567853A/en
Publication of JPS6142301B2 publication Critical patent/JPS6142301B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To facilitate an easy debug for the program as well as the fault retrieval of the device by securing an automatic memorization for the career of the order address at the jump time and in synchronization with the order execution.
CONSTITUTION: FF14 is set in the writing mode, and line 20 is energized when the jump occurs at process oart 2. A comparison is given between the current executing address information supplied to line 27 from part 2 and jump address register 11 at comparator unit 4. And in case no coincidence is obtained, the current executing address on line 27 is set to register 11. The contents of address register 13 receives +1 by output 30 of gate 16 due to the signal on line 38, and furthermore the current executing address is memorized in the address of memory 10 designated by address register 13 and via memory control signal 35. After this, if the signal occurs to line 20, the same action as the above is given to memorize the new jump address in memory 10. And memory 10 is read out by setting FF15.
COPYRIGHT: (C)1980,JPO&Japio
JP14144678A 1978-11-16 1978-11-16 Logic device Granted JPS5567853A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14144678A JPS5567853A (en) 1978-11-16 1978-11-16 Logic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14144678A JPS5567853A (en) 1978-11-16 1978-11-16 Logic device

Publications (2)

Publication Number Publication Date
JPS5567853A true JPS5567853A (en) 1980-05-22
JPS6142301B2 JPS6142301B2 (en) 1986-09-20

Family

ID=15292110

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14144678A Granted JPS5567853A (en) 1978-11-16 1978-11-16 Logic device

Country Status (1)

Country Link
JP (1) JPS5567853A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58103047A (en) * 1981-12-16 1983-06-18 Hitachi Ltd Instruction tracing device
JPS6244848A (en) * 1985-08-23 1987-02-26 Hitachi Electronics Eng Co Ltd Compressing device for recording information in computer program tracer
JPS62111334A (en) * 1985-11-11 1987-05-22 Hitachi Electronics Eng Co Ltd Compressing device for recording information in computer program tracer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5040255A (en) * 1973-08-16 1975-04-12

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5040255A (en) * 1973-08-16 1975-04-12

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58103047A (en) * 1981-12-16 1983-06-18 Hitachi Ltd Instruction tracing device
JPS6244848A (en) * 1985-08-23 1987-02-26 Hitachi Electronics Eng Co Ltd Compressing device for recording information in computer program tracer
JPS62111334A (en) * 1985-11-11 1987-05-22 Hitachi Electronics Eng Co Ltd Compressing device for recording information in computer program tracer

Also Published As

Publication number Publication date
JPS6142301B2 (en) 1986-09-20

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