JPS5568741A - Counter circuit - Google Patents

Counter circuit

Info

Publication number
JPS5568741A
JPS5568741A JP14298378A JP14298378A JPS5568741A JP S5568741 A JPS5568741 A JP S5568741A JP 14298378 A JP14298378 A JP 14298378A JP 14298378 A JP14298378 A JP 14298378A JP S5568741 A JPS5568741 A JP S5568741A
Authority
JP
Japan
Prior art keywords
lower limit
limit value
coincidence
circuits
contents
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14298378A
Other languages
Japanese (ja)
Inventor
Sukeyuki Tofuku
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14298378A priority Critical patent/JPS5568741A/en
Publication of JPS5568741A publication Critical patent/JPS5568741A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains

Landscapes

  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To secure the up-down counting between the upper and lower limit value by stopping the count contents at the prescribed upper and lower limit value each via the 1st and 2nd coincidence circuits. CONSTITUTION:Up-down counter 1 contains up-pulse input terminal 2 and down- pulse input terminal 3. And coincidence circuits 6 and 7 detect the coincidence of the count contents with the upper and lower limit value each. With the detection output of circuits 6 and 7, the introduction of the pulses is inhibited from outside, and thus the contents of cunter 1 can be stopped at the prescribed upper or lower limit value. As a result, the up-down counting is possible between the upper and lower limit value.
JP14298378A 1978-11-20 1978-11-20 Counter circuit Pending JPS5568741A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14298378A JPS5568741A (en) 1978-11-20 1978-11-20 Counter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14298378A JPS5568741A (en) 1978-11-20 1978-11-20 Counter circuit

Publications (1)

Publication Number Publication Date
JPS5568741A true JPS5568741A (en) 1980-05-23

Family

ID=15328193

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14298378A Pending JPS5568741A (en) 1978-11-20 1978-11-20 Counter circuit

Country Status (1)

Country Link
JP (1) JPS5568741A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63111028U (en) * 1987-01-07 1988-07-16

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5010548A (en) * 1973-05-24 1975-02-03
JPS52147955A (en) * 1976-06-03 1977-12-08 Toshiba Corp Pulse duration variable circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5010548A (en) * 1973-05-24 1975-02-03
JPS52147955A (en) * 1976-06-03 1977-12-08 Toshiba Corp Pulse duration variable circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63111028U (en) * 1987-01-07 1988-07-16

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