JPS5569860A - Clock margin setting system - Google Patents
Clock margin setting systemInfo
- Publication number
- JPS5569860A JPS5569860A JP14377078A JP14377078A JPS5569860A JP S5569860 A JPS5569860 A JP S5569860A JP 14377078 A JP14377078 A JP 14377078A JP 14377078 A JP14377078 A JP 14377078A JP S5569860 A JPS5569860 A JP S5569860A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- pulse
- clock
- circuits
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53143770A JPS603221B2 (ja) | 1978-11-21 | 1978-11-21 | クロツク・マ−ジン試験方式 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53143770A JPS603221B2 (ja) | 1978-11-21 | 1978-11-21 | クロツク・マ−ジン試験方式 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5569860A true JPS5569860A (en) | 1980-05-26 |
| JPS603221B2 JPS603221B2 (ja) | 1985-01-26 |
Family
ID=15346611
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP53143770A Expired JPS603221B2 (ja) | 1978-11-21 | 1978-11-21 | クロツク・マ−ジン試験方式 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS603221B2 (ja) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6015727A (ja) * | 1983-07-05 | 1985-01-26 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | データ経路の圧迫方法 |
| JPS625445A (ja) * | 1985-07-01 | 1987-01-12 | Nec Corp | 情報処理装置 |
-
1978
- 1978-11-21 JP JP53143770A patent/JPS603221B2/ja not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6015727A (ja) * | 1983-07-05 | 1985-01-26 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | データ経路の圧迫方法 |
| JPS625445A (ja) * | 1985-07-01 | 1987-01-12 | Nec Corp | 情報処理装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS603221B2 (ja) | 1985-01-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0126163A4 (en) | CONTROLLER WITH STATUS DISPLAY UNIT. | |
| JPS5631103A (en) | Sequence control device | |
| JPS5554403A (en) | Zero adjuster | |
| JPS5323243A (en) | Interruption control circuit | |
| JPS5781651A (en) | Priority controlling system of information processor | |
| JPS57153324A (en) | Interruption controlling adaptor | |
| JPS5584093A (en) | Bubble memory test equipment | |
| JPS5538604A (en) | Memory device | |
| JPS5373324A (en) | Controlling device of pulse width controller inverters | |
| JPS5363829A (en) | Generation control system of interrupt signal and interrupt circuit its execution | |
| JPS53117956A (en) | Timing signal generator | |
| JPS5271218A (en) | Pitch controller for electronic musical instruments | |
| JPS5352320A (en) | Output control circuit | |
| JPS5510684A (en) | Timing generating circuit | |
| JPS5323552A (en) | Pulse row detection circuit | |
| JPS57130135A (en) | Timing control circuit | |
| JPS5242353A (en) | Timing control circuit by delay element | |
| JPS53128237A (en) | Floppy disk control device | |
| JPS53146549A (en) | Gate circuit | |
| JPS53109452A (en) | Timing signal generating circuit | |
| JPS55132155A (en) | Phase control circuit | |
| JPS5525143A (en) | Data transfer controller | |
| JPS53130939A (en) | Magnetic bubble memory element | |
| JPS53135514A (en) | Signal decision circuit of automatic channel selection device | |
| JPS54123848A (en) | Test equipment for digital control circuit |