JPS5570920A - Memory control system - Google Patents

Memory control system

Info

Publication number
JPS5570920A
JPS5570920A JP14318178A JP14318178A JPS5570920A JP S5570920 A JPS5570920 A JP S5570920A JP 14318178 A JP14318178 A JP 14318178A JP 14318178 A JP14318178 A JP 14318178A JP S5570920 A JPS5570920 A JP S5570920A
Authority
JP
Japan
Prior art keywords
memory
data
fed
jitter
readout
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14318178A
Other languages
Japanese (ja)
Other versions
JPH0142069B2 (en
Inventor
Harukuni Kohari
Yasuhiro Yamada
Susumu Suzuki
Chitoshi Hibino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victor Company of Japan Ltd
Original Assignee
Victor Company of Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company of Japan Ltd filed Critical Victor Company of Japan Ltd
Priority to JP14318178A priority Critical patent/JPS5570920A/en
Priority to US06/095,553 priority patent/US4333160A/en
Priority to DE19792946702 priority patent/DE2946702A1/en
Priority to GB7940028A priority patent/GB2039193B/en
Publication of JPS5570920A publication Critical patent/JPS5570920A/en
Publication of JPH0142069B2 publication Critical patent/JPH0142069B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Error Detection And Correction (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)

Abstract

PURPOSE: To obtain desired data without jitter with readout and correction in the speed accompanying jitter for the data and correction signal and with write-in to the origianl memory area.
CONSTITUTION: The clock pulse fw having the same jitter as the reproduced digital signal is fed to the counter 20 having the same capacity as the total memory capacity of the memory 11 and the addition corresponding to the write-in address and readout address for error correction at the adder 21 for the count output is made, the output of addition is fed to the memory 11 and written in the divided memory capacities 16W19. Further, during write-in, the same pulse as pulse fw is fed to the counter 22, the decoder output is added 23, and readout is made from the parts 16W19. In this case, the data in error is corrected through the modulo addition 2 and the corresoponding part is written in the parts 16W18. With the performance of this operation every 1H period, the corrected data is stored.
COPYRIGHT: (C)1980,JPO&Japio
JP14318178A 1978-11-20 1978-11-20 Memory control system Granted JPS5570920A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP14318178A JPS5570920A (en) 1978-11-20 1978-11-20 Memory control system
US06/095,553 US4333160A (en) 1978-11-20 1979-11-19 Memory control system
DE19792946702 DE2946702A1 (en) 1978-11-20 1979-11-20 MEMORY CONTROL DEVICE
GB7940028A GB2039193B (en) 1978-11-20 1979-11-20 Memory control system for interleaving digital signals

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14318178A JPS5570920A (en) 1978-11-20 1978-11-20 Memory control system

Publications (2)

Publication Number Publication Date
JPS5570920A true JPS5570920A (en) 1980-05-28
JPH0142069B2 JPH0142069B2 (en) 1989-09-08

Family

ID=15332765

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14318178A Granted JPS5570920A (en) 1978-11-20 1978-11-20 Memory control system

Country Status (1)

Country Link
JP (1) JPS5570920A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58125210A (en) * 1982-01-20 1983-07-26 Pioneer Electronic Corp Device for producing memory address information signal
JPS58161114A (en) * 1982-03-19 1983-09-24 Pioneer Electronic Corp Memory address information signal generating device
JPS59198513A (en) * 1983-04-26 1984-11-10 Nec Corp Digital signal processor
JPS6079564A (en) * 1983-10-05 1985-05-07 Nippon Gakki Seizo Kk Address control circuit of dad player
JPS60256990A (en) * 1984-06-01 1985-12-18 Toshiba Corp Magnetic recording device and magnetic reproducing device
JPS61180905A (en) * 1985-02-06 1986-08-13 Matsushita Electric Ind Co Ltd Digital data recording and reproducing device
JPS61288522A (en) * 1985-06-14 1986-12-18 Hitachi Ltd Error correcting device
JPS6286584A (en) * 1985-10-11 1987-04-21 Hitachi Ltd Digital signal recording and reproducing device
JPS62202359A (en) * 1986-02-28 1987-09-07 Sony Corp Decoder
JPS63149919A (en) * 1986-12-12 1988-06-22 Mitsubishi Electric Corp Memory control circuit for pcm equipment

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5522244A (en) * 1978-07-28 1980-02-16 Sanyo Electric Co Ltd Memory system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5522244A (en) * 1978-07-28 1980-02-16 Sanyo Electric Co Ltd Memory system

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58125210A (en) * 1982-01-20 1983-07-26 Pioneer Electronic Corp Device for producing memory address information signal
JPS58161114A (en) * 1982-03-19 1983-09-24 Pioneer Electronic Corp Memory address information signal generating device
JPS59198513A (en) * 1983-04-26 1984-11-10 Nec Corp Digital signal processor
JPS6079564A (en) * 1983-10-05 1985-05-07 Nippon Gakki Seizo Kk Address control circuit of dad player
JPS60256990A (en) * 1984-06-01 1985-12-18 Toshiba Corp Magnetic recording device and magnetic reproducing device
JPS61180905A (en) * 1985-02-06 1986-08-13 Matsushita Electric Ind Co Ltd Digital data recording and reproducing device
JPS61288522A (en) * 1985-06-14 1986-12-18 Hitachi Ltd Error correcting device
JPS6286584A (en) * 1985-10-11 1987-04-21 Hitachi Ltd Digital signal recording and reproducing device
JPS62202359A (en) * 1986-02-28 1987-09-07 Sony Corp Decoder
JPS63149919A (en) * 1986-12-12 1988-06-22 Mitsubishi Electric Corp Memory control circuit for pcm equipment

Also Published As

Publication number Publication date
JPH0142069B2 (en) 1989-09-08

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