JPS5573155A - Disturbing pulse suppression device for fm stereo receiver - Google Patents

Disturbing pulse suppression device for fm stereo receiver

Info

Publication number
JPS5573155A
JPS5573155A JP14638378A JP14638378A JPS5573155A JP S5573155 A JPS5573155 A JP S5573155A JP 14638378 A JP14638378 A JP 14638378A JP 14638378 A JP14638378 A JP 14638378A JP S5573155 A JPS5573155 A JP S5573155A
Authority
JP
Japan
Prior art keywords
circuit
pulse
disturbing
disturbing pulse
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14638378A
Other languages
Japanese (ja)
Other versions
JPS5851703B2 (en
Inventor
Junichi Hikita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Toyo Electronics Industry Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd, Toyo Electronics Industry Corp filed Critical Rohm Co Ltd
Priority to JP14638378A priority Critical patent/JPS5851703B2/en
Publication of JPS5573155A publication Critical patent/JPS5573155A/en
Publication of JPS5851703B2 publication Critical patent/JPS5851703B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Noise Elimination (AREA)
  • Stereo-Broadcasting Methods (AREA)

Abstract

PURPOSE: To secure the constitution of the disturbing pulse suppression circuit in a simple way by securing suppression for demodulation of the disturbing pulse via the circuit constituted in a digital way and at the same time doubling the function of the demodulator circuit.
CONSTITUTION: In case disturbing pulse P is contained near the high peak value of the subcarrier, the pulse is sample-held directly by 1st sample holding circuit 6 and then delivered to 2nd sample holding circuit 7. Pulse P is then detected through disturbing pulse detector circuit 12, and thus pulse generator circuit 13 is triggered. As a result, output d is supplied to gate circuit 9 to close the gate for the fixed time. Thus subsequent pulse b1 is unable to pass through circuit 9, and as a result circuit 7 holds continuously the so far holding value for the period of pulse generation. Thus pulse P is not held by circuit 7. And in case pulse P is contained near the low peak value of the subcarrier, the same operation is secured to close gate circuit 10.
COPYRIGHT: (C)1980,JPO&Japio
JP14638378A 1978-11-27 1978-11-27 Interference pulse suppression device for FM stereo receiver Expired JPS5851703B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14638378A JPS5851703B2 (en) 1978-11-27 1978-11-27 Interference pulse suppression device for FM stereo receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14638378A JPS5851703B2 (en) 1978-11-27 1978-11-27 Interference pulse suppression device for FM stereo receiver

Publications (2)

Publication Number Publication Date
JPS5573155A true JPS5573155A (en) 1980-06-02
JPS5851703B2 JPS5851703B2 (en) 1983-11-17

Family

ID=15406455

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14638378A Expired JPS5851703B2 (en) 1978-11-27 1978-11-27 Interference pulse suppression device for FM stereo receiver

Country Status (1)

Country Link
JP (1) JPS5851703B2 (en)

Also Published As

Publication number Publication date
JPS5851703B2 (en) 1983-11-17

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