JPS5574647A - Initializing system for microprocessor - Google Patents

Initializing system for microprocessor

Info

Publication number
JPS5574647A
JPS5574647A JP14740878A JP14740878A JPS5574647A JP S5574647 A JPS5574647 A JP S5574647A JP 14740878 A JP14740878 A JP 14740878A JP 14740878 A JP14740878 A JP 14740878A JP S5574647 A JPS5574647 A JP S5574647A
Authority
JP
Japan
Prior art keywords
microprocessor
control memory
instruction
meaning
fed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14740878A
Other languages
Japanese (ja)
Inventor
Yoshio Hirota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14740878A priority Critical patent/JPS5574647A/en
Publication of JPS5574647A publication Critical patent/JPS5574647A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable to initialize the microprocessor in a short time, even if the microprocessor incorporates the control memory address, by not taking the synchronism with other as problem.
CONSTITUTION: The initializing signal 5 fed to the S terminal of FF4 externally and the output B to the gate 6 is caused by setting this. The non-meaning signal 7 is fed to the separate terminal of the said gate 6, the non-meaning instruction 7 from this reaches the microprocessor 2 via the gate 8 and the non-meaning instruction such as C is executed. The specific insturction 10 enters the control memory section 1 every given block and this is read out at the control memory address 3 as D. The specific instruction 10 from the control memory section 1 is fed to the terminal R of FF4 and this is cleared. The non-meaning instruction 7 is not transferred and it is trnsferred to the specific instruction processor 2. Further, by executing this, the address 3 is taken as the start address of the initializing routine.
COPYRIGHT: (C)1980,JPO&Japio
JP14740878A 1978-11-29 1978-11-29 Initializing system for microprocessor Pending JPS5574647A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14740878A JPS5574647A (en) 1978-11-29 1978-11-29 Initializing system for microprocessor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14740878A JPS5574647A (en) 1978-11-29 1978-11-29 Initializing system for microprocessor

Publications (1)

Publication Number Publication Date
JPS5574647A true JPS5574647A (en) 1980-06-05

Family

ID=15429614

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14740878A Pending JPS5574647A (en) 1978-11-29 1978-11-29 Initializing system for microprocessor

Country Status (1)

Country Link
JP (1) JPS5574647A (en)

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