JPS557614A - Digital clock - Google Patents

Digital clock

Info

Publication number
JPS557614A
JPS557614A JP7949578A JP7949578A JPS557614A JP S557614 A JPS557614 A JP S557614A JP 7949578 A JP7949578 A JP 7949578A JP 7949578 A JP7949578 A JP 7949578A JP S557614 A JPS557614 A JP S557614A
Authority
JP
Japan
Prior art keywords
circuit
output
frequency
pulse
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7949578A
Other languages
Japanese (ja)
Inventor
Akinobu Masuko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP7949578A priority Critical patent/JPS557614A/en
Publication of JPS557614A publication Critical patent/JPS557614A/en
Pending legal-status Critical Current

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  • Electric Clocks (AREA)

Abstract

PURPOSE: To enable normal time clock even with AC power supply failure, by taking the output pulse of the oscillator operated with AC input and the built-in cells as the reference clock of time count operation.
CONSTITUTION: When the input of AC power 1 is absent, the voltage by the battery 5 is fed to the circuit with the forward bias of the diode D4, and the initialize circuit 6 keeps the output of the logic level "1". On the other hand, since the output of the Schmitt trigger circuit 11 rises from the level "0" to "1", the monostable multivibrators 12 and 13 are operated, and the output pulse of the oscillator 15 is given to the gate circuit 14 via the Schmitt trigger circuit 16, the leading resets FF7, and the inversion output is fed to the frequency selection gate circuit 25 to select the counter 23 with the 50 Hz counter. Further, the pulse in frequency 320 Hz in the circuit 16 is counted with the counter 17, and it is frequency-divided into 1/6400 being the sub-reference pulse in frequency 50 Hz. Accordingly, even if AC power is in failure, normal time count operation can be made.
COPYRIGHT: (C)1980,JPO&Japio
JP7949578A 1978-06-30 1978-06-30 Digital clock Pending JPS557614A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7949578A JPS557614A (en) 1978-06-30 1978-06-30 Digital clock

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7949578A JPS557614A (en) 1978-06-30 1978-06-30 Digital clock

Publications (1)

Publication Number Publication Date
JPS557614A true JPS557614A (en) 1980-01-19

Family

ID=13691482

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7949578A Pending JPS557614A (en) 1978-06-30 1978-06-30 Digital clock

Country Status (1)

Country Link
JP (1) JPS557614A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58216966A (en) * 1982-06-11 1983-12-16 Toshiba Corp Circuit for detecting power failure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58216966A (en) * 1982-06-11 1983-12-16 Toshiba Corp Circuit for detecting power failure

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