JPS5576456A - Microprocessor test unit - Google Patents

Microprocessor test unit

Info

Publication number
JPS5576456A
JPS5576456A JP15075178A JP15075178A JPS5576456A JP S5576456 A JPS5576456 A JP S5576456A JP 15075178 A JP15075178 A JP 15075178A JP 15075178 A JP15075178 A JP 15075178A JP S5576456 A JPS5576456 A JP S5576456A
Authority
JP
Japan
Prior art keywords
chip
processor
microprocessor
action
tested
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15075178A
Other languages
Japanese (ja)
Other versions
JPS59852B2 (en
Inventor
Osamu Koichi
Kensaku Wada
Koichi Yuasa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53150751A priority Critical patent/JPS59852B2/en
Publication of JPS5576456A publication Critical patent/JPS5576456A/en
Publication of JPS59852B2 publication Critical patent/JPS59852B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To secure the analysis for the defective areas of the microprocessor to be tested by securing latching by FF when the tested microprocessor's program counter has an overflow to stop the operation of the evaluator chip.
CONSTITUTION: Evaluator chip 11 features the same function as tested microprocessor 13. For this chip 11, the test program combined via the address bus and the data bus is stored in external program memory 12. Then the synchronous and parallel action is given to both processor 13 and chip 11 while the action of ROM of processor 11 is being suppressed by control circuit 14. Furthermore, in case the program counter of processor 13 has an overflow, it is latched by FF15. And the output stops the action of chip 11. Thus the defective areas of processor 13 can be analyzed based on the address of chip 11 when stopped.
COPYRIGHT: (C)1980,JPO&Japio
JP53150751A 1978-12-05 1978-12-05 Microprocessor test equipment Expired JPS59852B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53150751A JPS59852B2 (en) 1978-12-05 1978-12-05 Microprocessor test equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53150751A JPS59852B2 (en) 1978-12-05 1978-12-05 Microprocessor test equipment

Publications (2)

Publication Number Publication Date
JPS5576456A true JPS5576456A (en) 1980-06-09
JPS59852B2 JPS59852B2 (en) 1984-01-09

Family

ID=15503612

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53150751A Expired JPS59852B2 (en) 1978-12-05 1978-12-05 Microprocessor test equipment

Country Status (1)

Country Link
JP (1) JPS59852B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100359333C (en) * 2004-05-26 2008-01-02 华为技术有限公司 A Simulation Test Method Applied to Chip

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100359333C (en) * 2004-05-26 2008-01-02 华为技术有限公司 A Simulation Test Method Applied to Chip

Also Published As

Publication number Publication date
JPS59852B2 (en) 1984-01-09

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