JPS5577071A - Address converter - Google Patents

Address converter

Info

Publication number
JPS5577071A
JPS5577071A JP14996578A JP14996578A JPS5577071A JP S5577071 A JPS5577071 A JP S5577071A JP 14996578 A JP14996578 A JP 14996578A JP 14996578 A JP14996578 A JP 14996578A JP S5577071 A JPS5577071 A JP S5577071A
Authority
JP
Japan
Prior art keywords
address
insignificant
buffer
codes
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14996578A
Other languages
Japanese (ja)
Inventor
Yoshio Oshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14996578A priority Critical patent/JPS5577071A/en
Publication of JPS5577071A publication Critical patent/JPS5577071A/en
Pending legal-status Critical Current

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To register insignificant codes in an address conversion buffer at a high speed by giving reference address of address conversion buffer from an address counter circuit as well.
CONSTITUTION: Reference addresses of address conversion buffer 10 can be given from not only outputs from logical address register 6 but also those of address counter circuit 31, and they are changed over under conditions where insignificant codes are registered in buffer 10. Further, counter 31, composed of a counter, for example, covers all addresses of buffer 10. As a result, the updata of the reference address of an insignificant code in buffer 10 is made independent from machine cycles of arithmetic control part 30 during insignificant code registration and counter circuit 31 can update the reference address. Therefore, insignificant codes can be registered at a high speed.
COPYRIGHT: (C)1980,JPO&Japio
JP14996578A 1978-12-06 1978-12-06 Address converter Pending JPS5577071A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14996578A JPS5577071A (en) 1978-12-06 1978-12-06 Address converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14996578A JPS5577071A (en) 1978-12-06 1978-12-06 Address converter

Publications (1)

Publication Number Publication Date
JPS5577071A true JPS5577071A (en) 1980-06-10

Family

ID=15486472

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14996578A Pending JPS5577071A (en) 1978-12-06 1978-12-06 Address converter

Country Status (1)

Country Link
JP (1) JPS5577071A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57113476A (en) * 1980-12-29 1982-07-14 Fujitsu Ltd Tlb controlling system
JPS61169950A (en) * 1985-01-22 1986-07-31 Fujitsu Ltd Buffer invalidating system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50722A (en) * 1973-05-02 1975-01-07
JPS52142440A (en) * 1976-05-21 1977-11-28 Fujitsu Ltd Data processing system embodied partial purge function

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50722A (en) * 1973-05-02 1975-01-07
JPS52142440A (en) * 1976-05-21 1977-11-28 Fujitsu Ltd Data processing system embodied partial purge function

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57113476A (en) * 1980-12-29 1982-07-14 Fujitsu Ltd Tlb controlling system
JPS61169950A (en) * 1985-01-22 1986-07-31 Fujitsu Ltd Buffer invalidating system

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