JPS5578565A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPS5578565A JPS5578565A JP15280978A JP15280978A JPS5578565A JP S5578565 A JPS5578565 A JP S5578565A JP 15280978 A JP15280978 A JP 15280978A JP 15280978 A JP15280978 A JP 15280978A JP S5578565 A JPS5578565 A JP S5578565A
- Authority
- JP
- Japan
- Prior art keywords
- regions
- substrate
- grooves
- semiconductor layer
- semiconductor layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
PURPOSE:To make alignment of individual portions easy and to readily manufacture highly integrated memories by utilizing complete or incomplete V grooves used for gates or isolation. CONSTITUTION:An inversely-conductive semiconductor layer 2 is formed on a conductive-type semiconductor substrate 1. Regions 3a-3d whose conductivity is the same as that of the substrate 1 are partially formed on the surface of the semiconductor layer 2. Complete V grooves 4a-4c and incomplete V grooves 4d- 4e, which are surrounded by regions 3a-3d, and whose bottoms reach the inside of the substrate 1, are further formed. Insulating gates 6a, 6b, 6c and 6d are provided on said grooves. The first FET is formed by the semiconductor layer 2, the substrate 1, and the semiconductor layers 2a-2d on which regions 3a-3d are formed; and the second FET is formed by the substrate 1, the semiconductor layers 2a-2d, and the regions 3a-3d. The semiconductor layers 2a-2d which are isolated from the surrounding portion, on which the regions 3a-3d are formed, are made to be an electric-charge storage region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15280978A JPS5578565A (en) | 1978-12-09 | 1978-12-09 | Semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15280978A JPS5578565A (en) | 1978-12-09 | 1978-12-09 | Semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5578565A true JPS5578565A (en) | 1980-06-13 |
| JPS6136712B2 JPS6136712B2 (en) | 1986-08-20 |
Family
ID=15548619
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15280978A Granted JPS5578565A (en) | 1978-12-09 | 1978-12-09 | Semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5578565A (en) |
-
1978
- 1978-12-09 JP JP15280978A patent/JPS5578565A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6136712B2 (en) | 1986-08-20 |
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