JPS5578566A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5578566A
JPS5578566A JP15191878A JP15191878A JPS5578566A JP S5578566 A JPS5578566 A JP S5578566A JP 15191878 A JP15191878 A JP 15191878A JP 15191878 A JP15191878 A JP 15191878A JP S5578566 A JPS5578566 A JP S5578566A
Authority
JP
Japan
Prior art keywords
semiconductor layer
contact
layer
diffused
laser light
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15191878A
Other languages
Japanese (ja)
Inventor
Hisakazu Iizuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15191878A priority Critical patent/JPS5578566A/en
Publication of JPS5578566A publication Critical patent/JPS5578566A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE: To make the control of contact resistance between two layers possible by illuminating pulse laser light on a contact region through the second semiconductor layer, in the case electrical contact is obtained by forming the second semiconductor layer on a portion of the first semiconductor layer.
CONSTITUTION: A field oxide film 2 is formed on a p-type Si substrate 1 which is the first semiconductor layer. After a portion of the film 2 has been removed, a gate oxide film 3 is formed, and a direct-contact forming region 4 is formed. Then, a polycrystal Si layer 5 which is the second semiconductor layer is deposited all over the surface, patterning is made by a photoresist 6, and a gate electrode 8 and wiring layers 9 are formed from the Si layer 5. Thereafter n-type impurities are diffused to form a source 10 and a drain 11. At this time, the impurities are diffused into the electrode 8 and the wiring layers 9 to make them function as a conductor. Then, pulsed laser light 12 is illuminated on at least the contact region, i.e., the direct contact portion.
COPYRIGHT: (C)1980,JPO&Japio
JP15191878A 1978-12-11 1978-12-11 Manufacture of semiconductor device Pending JPS5578566A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15191878A JPS5578566A (en) 1978-12-11 1978-12-11 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15191878A JPS5578566A (en) 1978-12-11 1978-12-11 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5578566A true JPS5578566A (en) 1980-06-13

Family

ID=15529036

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15191878A Pending JPS5578566A (en) 1978-12-11 1978-12-11 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5578566A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS566434A (en) * 1979-06-28 1981-01-23 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS566434A (en) * 1979-06-28 1981-01-23 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device

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