JPS5579525A - Flip-flop circuit - Google Patents

Flip-flop circuit

Info

Publication number
JPS5579525A
JPS5579525A JP15353978A JP15353978A JPS5579525A JP S5579525 A JPS5579525 A JP S5579525A JP 15353978 A JP15353978 A JP 15353978A JP 15353978 A JP15353978 A JP 15353978A JP S5579525 A JPS5579525 A JP S5579525A
Authority
JP
Japan
Prior art keywords
master
slave
changes
outputs
inverters
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15353978A
Other languages
Japanese (ja)
Inventor
Yasoji Suzuki
Minoru Takada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15353978A priority Critical patent/JPS5579525A/en
Priority to US06/101,103 priority patent/US4356411A/en
Publication of JPS5579525A publication Critical patent/JPS5579525A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3562—Bistable circuits of the primary-secondary type

Landscapes

  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To attain high-speed operation, high integration and low power consumption by constituting an FF circuit by connecting the output of master FF composed of two C-MOS inverters and transistors Tr to slave FF of similar elements. CONSTITUTION:Master FF consists of FF element 74 of C-MOS inverters 47 and 52, and Trs 53-54, and slave FF, composed of FF element 67 of C-MOS inverters 61 and 66, and Trs 68-71, is connected in series to master FF. Clock signal CK is applied to a fixed Tr gate and outputs Q's and Qs of slave FF are passed through inverters 72 and 73 to obtain outputs Q and Q', thereby constituting an FF circuit. In an initial state, signal CK is ''0'' while outputs QM and QS of master FF are ''0'' and ''1'' respectively and when CK changes into ''1'', QM becomes ''1'' and QS is ''1''. Once CK changes into ''0'', QS also changes into ''0''. In this constitution, an inverter of large Tr is unneeded since no out-of-phase signal is used, so that the advantage in low power consumption and high integration can be obtained. In addition, the response of variation in output with a clock is quick.
JP15353978A 1978-12-12 1978-12-12 Flip-flop circuit Pending JPS5579525A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP15353978A JPS5579525A (en) 1978-12-12 1978-12-12 Flip-flop circuit
US06/101,103 US4356411A (en) 1978-12-12 1979-12-07 Flip-flop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15353978A JPS5579525A (en) 1978-12-12 1978-12-12 Flip-flop circuit

Publications (1)

Publication Number Publication Date
JPS5579525A true JPS5579525A (en) 1980-06-16

Family

ID=15564720

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15353978A Pending JPS5579525A (en) 1978-12-12 1978-12-12 Flip-flop circuit

Country Status (1)

Country Link
JP (1) JPS5579525A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0905893A1 (en) * 1997-09-30 1999-03-31 STMicroelectronics SA Controlled transparency flipflop operating with a low swing clock signal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0905893A1 (en) * 1997-09-30 1999-03-31 STMicroelectronics SA Controlled transparency flipflop operating with a low swing clock signal

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