JPS5579559A - Facsimile circuit controller - Google Patents

Facsimile circuit controller

Info

Publication number
JPS5579559A
JPS5579559A JP15403778A JP15403778A JPS5579559A JP S5579559 A JPS5579559 A JP S5579559A JP 15403778 A JP15403778 A JP 15403778A JP 15403778 A JP15403778 A JP 15403778A JP S5579559 A JPS5579559 A JP S5579559A
Authority
JP
Japan
Prior art keywords
circuit
memory
coordinate
counter
common
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15403778A
Other languages
Japanese (ja)
Other versions
JPS6024623B2 (en
Inventor
Yasuhiro Inoue
Toshishige Fukuda
Shizuo Irisa
Sadami Kurihara
Takashi Kawade
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
NTT Inc
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP53154037A priority Critical patent/JPS6024623B2/en
Publication of JPS5579559A publication Critical patent/JPS5579559A/en
Publication of JPS6024623B2 publication Critical patent/JPS6024623B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Facsimiles In General (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE: To realize a miniature and low-priced integrated circuit by reducing counters in number by providing a common counter to a circuit coordinate part and common decoding part.
CONSTITUTION: When a picture signal decoded by common decoding part 15 is supplied to one memory 23 by way of AND circuit 25 and switch S1, decoding part 15 assigns circuit coordinate part 14. Next, a write address is given from counter 35 via AND circuit 33 and switch S13 to store the picture signal in memory 23 via circuit 25, and a read address is given to the other memory 21 from counter 31 via switch S11 to send the contents of memory 21 to a facsimile terminal via switch S2. In this way, assignment is done covering addresses AD0∼ADn by sequentially shifting to write memories of coordinate parts 141∼14n. Then, a pair of memory read addresses of coordinate parts 14 are given by common counter 31 provided to each coordinate part and for write addresses, common counter 35 provided to the decoding part can be utilized.
COPYRIGHT: (C)1980,JPO&Japio
JP53154037A 1978-12-12 1978-12-12 Facsimile line control device Expired JPS6024623B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53154037A JPS6024623B2 (en) 1978-12-12 1978-12-12 Facsimile line control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53154037A JPS6024623B2 (en) 1978-12-12 1978-12-12 Facsimile line control device

Publications (2)

Publication Number Publication Date
JPS5579559A true JPS5579559A (en) 1980-06-16
JPS6024623B2 JPS6024623B2 (en) 1985-06-13

Family

ID=15575526

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53154037A Expired JPS6024623B2 (en) 1978-12-12 1978-12-12 Facsimile line control device

Country Status (1)

Country Link
JP (1) JPS6024623B2 (en)

Also Published As

Publication number Publication date
JPS6024623B2 (en) 1985-06-13

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