JPS5580161A - Normally monitoring system of microcomputer - Google Patents

Normally monitoring system of microcomputer

Info

Publication number
JPS5580161A
JPS5580161A JP15307878A JP15307878A JPS5580161A JP S5580161 A JPS5580161 A JP S5580161A JP 15307878 A JP15307878 A JP 15307878A JP 15307878 A JP15307878 A JP 15307878A JP S5580161 A JPS5580161 A JP S5580161A
Authority
JP
Japan
Prior art keywords
circuit
program
results
operation processing
microcomputer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15307878A
Other languages
Japanese (ja)
Inventor
Tomio Chiba
Eizaburo Sako
Kazuhiro Sano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15307878A priority Critical patent/JPS5580161A/en
Publication of JPS5580161A publication Critical patent/JPS5580161A/en
Pending legal-status Critical Current

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Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To monitor normally a microcomputer independently of other system constitutions by causing a CPU to execute the program of an instruction circuit on the margin time of the operation processing for every sample of the microcomputer and comparing results in a comparator circuit.
CONSTITUTION: A unit which is constituted by an operation processing circuit, a program recording circuit, a data recording circuit and an I/O circuit and monitors normally the microcomputer, which subjects system information digitized and inputted from the object system to the operation processing at every sampling time and outputs required results, is provided with instruction circuit 10 where a program to check functions of operation results of CPU1 is stored. Further, comparator circuit 2 is provided which decides results of program execution for correctness when the program of instruction circuit 10 is executed by CPU1, and the operation processing of the program of instruction circuit 10 is executed by CPU1 on the margin time of the operation processing for every sampling under the control of I104 which inputs and outputs data, and normalcy of operation results are checked by circuit 20.
COPYRIGHT: (C)1980,JPO&Japio
JP15307878A 1978-12-13 1978-12-13 Normally monitoring system of microcomputer Pending JPS5580161A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15307878A JPS5580161A (en) 1978-12-13 1978-12-13 Normally monitoring system of microcomputer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15307878A JPS5580161A (en) 1978-12-13 1978-12-13 Normally monitoring system of microcomputer

Publications (1)

Publication Number Publication Date
JPS5580161A true JPS5580161A (en) 1980-06-17

Family

ID=15554488

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15307878A Pending JPS5580161A (en) 1978-12-13 1978-12-13 Normally monitoring system of microcomputer

Country Status (1)

Country Link
JP (1) JPS5580161A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01162695A (en) * 1987-12-16 1989-06-27 Hitachi Ltd elevator door control device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01162695A (en) * 1987-12-16 1989-06-27 Hitachi Ltd elevator door control device

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