JPS5582350A - Character display system - Google Patents

Character display system

Info

Publication number
JPS5582350A
JPS5582350A JP15780978A JP15780978A JPS5582350A JP S5582350 A JPS5582350 A JP S5582350A JP 15780978 A JP15780978 A JP 15780978A JP 15780978 A JP15780978 A JP 15780978A JP S5582350 A JPS5582350 A JP S5582350A
Authority
JP
Japan
Prior art keywords
memory
display
address
contents
refresh
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15780978A
Other languages
Japanese (ja)
Inventor
Seiji Ishimitsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP15780978A priority Critical patent/JPS5582350A/en
Publication of JPS5582350A publication Critical patent/JPS5582350A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To shorten the time until display of an operation result by reading out successively a display order address memory by a refresh control circuit and transferring contents to a display equipment.
CONSTITUTION: A display address where insertion, deletion and change will be operated is stored in cursor position register 6, and an address of dot refresh memory 2 where one-character share of patterns should be rewritten is determined, and one-character share of dot data to be inputted to this address is written. Meanwhile, contents of display order address memory 9 are written in the order to a new display while referring to the mode of operation and contents of register 6. Then, refresh memory control circuit 10 reads out successively memory 9 and transfers dot data to display equipment 4 with contents of memory 9 as address of memory 2. As a result, the time until display of the operation result can be shortened.
COPYRIGHT: (C)1980,JPO&Japio
JP15780978A 1978-12-18 1978-12-18 Character display system Pending JPS5582350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15780978A JPS5582350A (en) 1978-12-18 1978-12-18 Character display system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15780978A JPS5582350A (en) 1978-12-18 1978-12-18 Character display system

Publications (1)

Publication Number Publication Date
JPS5582350A true JPS5582350A (en) 1980-06-21

Family

ID=15657754

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15780978A Pending JPS5582350A (en) 1978-12-18 1978-12-18 Character display system

Country Status (1)

Country Link
JP (1) JPS5582350A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57161886A (en) * 1981-03-31 1982-10-05 Tokyo Shibaura Electric Co Display control system
JPS60121493A (en) * 1984-08-29 1985-06-28 株式会社東芝 Display control system
JPS60121496A (en) * 1984-08-29 1985-06-28 株式会社東芝 Display control system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57161886A (en) * 1981-03-31 1982-10-05 Tokyo Shibaura Electric Co Display control system
JPS60121493A (en) * 1984-08-29 1985-06-28 株式会社東芝 Display control system
JPS60121496A (en) * 1984-08-29 1985-06-28 株式会社東芝 Display control system

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