JPS5582518A - Level adjuster - Google Patents

Level adjuster

Info

Publication number
JPS5582518A
JPS5582518A JP15702278A JP15702278A JPS5582518A JP S5582518 A JPS5582518 A JP S5582518A JP 15702278 A JP15702278 A JP 15702278A JP 15702278 A JP15702278 A JP 15702278A JP S5582518 A JPS5582518 A JP S5582518A
Authority
JP
Japan
Prior art keywords
digital signal
attenuation
preset
input
rom20
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15702278A
Other languages
Japanese (ja)
Inventor
Koji Matsushima
Taiji Shimeki
Nobuyoshi Kihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP15702278A priority Critical patent/JPS5582518A/en
Publication of JPS5582518A publication Critical patent/JPS5582518A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/002—Control of digital or coded signals

Landscapes

  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To avoid the feeling of abnormal sound at signal interruption, by changing the input digital signal with the digital signal generator according to the attenuation characteristics preset. CONSTITUTION:When the instruction switch 14 is closed, pulse is fed to P-ROM20 in the preset interval from the clock generator 19. At P-ROM20, every input pulse, preset attenuation is produced and fed to the digital subtractor 15, and the differential signal component with the input digital signal from the terminal 11 passes through the data selector 16. Further, when the attenuation of the digital signal is greater than the input digital signal, the carryout of the subtractor 15 is 0 and the data selector 16 feeds the output of all 0 to the terminal 12.
JP15702278A 1978-12-19 1978-12-19 Level adjuster Pending JPS5582518A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15702278A JPS5582518A (en) 1978-12-19 1978-12-19 Level adjuster

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15702278A JPS5582518A (en) 1978-12-19 1978-12-19 Level adjuster

Publications (1)

Publication Number Publication Date
JPS5582518A true JPS5582518A (en) 1980-06-21

Family

ID=15640463

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15702278A Pending JPS5582518A (en) 1978-12-19 1978-12-19 Level adjuster

Country Status (1)

Country Link
JP (1) JPS5582518A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50131437A (en) * 1974-04-02 1975-10-17

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50131437A (en) * 1974-04-02 1975-10-17

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