JPS5582968A - Real time frequency analysis device - Google Patents

Real time frequency analysis device

Info

Publication number
JPS5582968A
JPS5582968A JP15637278A JP15637278A JPS5582968A JP S5582968 A JPS5582968 A JP S5582968A JP 15637278 A JP15637278 A JP 15637278A JP 15637278 A JP15637278 A JP 15637278A JP S5582968 A JPS5582968 A JP S5582968A
Authority
JP
Japan
Prior art keywords
circuit
signals
clock pulses
reading
period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15637278A
Other languages
Japanese (ja)
Inventor
Atsushi Sasaki
Masaharu Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15637278A priority Critical patent/JPS5582968A/en
Publication of JPS5582968A publication Critical patent/JPS5582968A/en
Pending legal-status Critical Current

Links

Landscapes

  • Measurement Of Mechanical Vibrations Or Ultrasonic Waves (AREA)

Abstract

PURPOSE: To set arbitary frequency analyzing width, by controlling clock pulses so that the memory reading time length of a time base converting circuit become constant, in a device applying heterodyne method.
CONSTITUTION: Input analog signals 6 are converted into digital signals by means of an A/D converting circuit, and applied to a time compression circuit 2. Signals 7 are recorded to an RAM forming the time compression circuit 2 in clock pulses with a period Tw at the circuit 2 while signals 8 reading time base-coverted are obtained in clock pulses, which period is shorter than the said clock pulses. The signals 8 are applied to a D/A converting circuit 3, and analysis output 11 is acquired through a heterodyne modulation circuit and band-pass filter circuit 5. If the frequency resolving width of the band-pass filter circuit 5 is Δf and the product of the reading word number and reading period TR of the RAM is fixed, frequency can be analyzed in resolving width decided by Δf×TR/Tw.
COPYRIGHT: (C)1980,JPO&Japio
JP15637278A 1978-12-20 1978-12-20 Real time frequency analysis device Pending JPS5582968A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15637278A JPS5582968A (en) 1978-12-20 1978-12-20 Real time frequency analysis device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15637278A JPS5582968A (en) 1978-12-20 1978-12-20 Real time frequency analysis device

Publications (1)

Publication Number Publication Date
JPS5582968A true JPS5582968A (en) 1980-06-23

Family

ID=15626305

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15637278A Pending JPS5582968A (en) 1978-12-20 1978-12-20 Real time frequency analysis device

Country Status (1)

Country Link
JP (1) JPS5582968A (en)

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