JPS5583330A - Automatic tuner circuit - Google Patents

Automatic tuner circuit

Info

Publication number
JPS5583330A
JPS5583330A JP15637578A JP15637578A JPS5583330A JP S5583330 A JPS5583330 A JP S5583330A JP 15637578 A JP15637578 A JP 15637578A JP 15637578 A JP15637578 A JP 15637578A JP S5583330 A JPS5583330 A JP S5583330A
Authority
JP
Japan
Prior art keywords
tuner
circuit
terminal
automatic
reception
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15637578A
Other languages
Japanese (ja)
Inventor
Masanori Kamiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15637578A priority Critical patent/JPS5583330A/en
Publication of JPS5583330A publication Critical patent/JPS5583330A/en
Pending legal-status Critical Current

Links

Landscapes

  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Abstract

PURPOSE: To prevent malfunction as to reception of a spurious signal by providing a method of lowering the gain of a tuner only while an automatic tuner circuit is in reception frequency sweep operation of the tuner.
CONSTITUTION: While a TV receiver is receiving a weak electric field, a high voltage is outputted to output terminal 15 of AGC circuit 7 to place transistor Tr12 in a cut-off state, and consequently the high voltage is applied to terminal 14 of tuner 2, so that tuner 2 will operate with its maximum sensitivity. Next, while an automatic tuner circuit is sweeping a reception frequency, Tr12 conducts by a signal appearing at terminal 13 of main body 11a of the automatic tuner circuit, and consequently no signal is inputted to detection circuit 4 to apply a voltage divided by resistances 16 and 17 to terminal 14 of tuner 2 even when a voltage at terminal 15 of circuit 7 is fixed high, so that the gain of tuner 2 will be attenuated. As a result, spurious generation is suppressed, so that malfunction as to reception of a spurious signal will never occur.
COPYRIGHT: (C)1980,JPO&Japio
JP15637578A 1978-12-20 1978-12-20 Automatic tuner circuit Pending JPS5583330A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15637578A JPS5583330A (en) 1978-12-20 1978-12-20 Automatic tuner circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15637578A JPS5583330A (en) 1978-12-20 1978-12-20 Automatic tuner circuit

Publications (1)

Publication Number Publication Date
JPS5583330A true JPS5583330A (en) 1980-06-23

Family

ID=15626370

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15637578A Pending JPS5583330A (en) 1978-12-20 1978-12-20 Automatic tuner circuit

Country Status (1)

Country Link
JP (1) JPS5583330A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6282812A (en) * 1985-10-08 1987-04-16 Matsushita Electric Ind Co Ltd automatic channel selection device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6282812A (en) * 1985-10-08 1987-04-16 Matsushita Electric Ind Co Ltd automatic channel selection device

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