JPS5583931A - Display control system - Google Patents

Display control system

Info

Publication number
JPS5583931A
JPS5583931A JP15629178A JP15629178A JPS5583931A JP S5583931 A JPS5583931 A JP S5583931A JP 15629178 A JP15629178 A JP 15629178A JP 15629178 A JP15629178 A JP 15629178A JP S5583931 A JPS5583931 A JP S5583931A
Authority
JP
Japan
Prior art keywords
data
character
control
counter
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15629178A
Other languages
Japanese (ja)
Inventor
Yoshihiko Nomi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15629178A priority Critical patent/JPS5583931A/en
Publication of JPS5583931A publication Critical patent/JPS5583931A/en
Pending legal-status Critical Current

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  • Digital Computer Display Output (AREA)

Abstract

PURPOSE: To increase both the processing speed and efficiency in case the character code is stored into the picture memory, by storing the control additional bit within the address same as each character code data and then carrying out the array control of the characters via the control additional bit.
CONSTITUTION: Display control unit 1 contains memory 2 which stores the control data to array the character data on the screen plus character generator 3 which delivers character pattern data S2 in response to character data S1 delivered from memory 2. Line control data S3 is supplied to line control bit detection circuit 4 and then supplied to binary counter 5 in the form of count pulse S5. Output S6 is compared with output S7 given from constant setting circuit 6 at comparator circuit 7. And S8 becomes "1" only when S6>S7 is satisfied, and S9 features the contrary relation to S8. Then S8 is supplied to counter 5 as the reset signal as well as to gate circuit 8. And counter 5 is reset when S8 is "1", and at the same time circuit 8 is opened. Then output S10 of display address counter 9 is put into register 10.
COPYRIGHT: (C)1980,JPO&Japio
JP15629178A 1978-12-20 1978-12-20 Display control system Pending JPS5583931A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15629178A JPS5583931A (en) 1978-12-20 1978-12-20 Display control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15629178A JPS5583931A (en) 1978-12-20 1978-12-20 Display control system

Publications (1)

Publication Number Publication Date
JPS5583931A true JPS5583931A (en) 1980-06-24

Family

ID=15624592

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15629178A Pending JPS5583931A (en) 1978-12-20 1978-12-20 Display control system

Country Status (1)

Country Link
JP (1) JPS5583931A (en)

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