JPS5585913A - Sequence control unit - Google Patents

Sequence control unit

Info

Publication number
JPS5585913A
JPS5585913A JP15850978A JP15850978A JPS5585913A JP S5585913 A JPS5585913 A JP S5585913A JP 15850978 A JP15850978 A JP 15850978A JP 15850978 A JP15850978 A JP 15850978A JP S5585913 A JPS5585913 A JP S5585913A
Authority
JP
Japan
Prior art keywords
input
area
output section
output
inputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15850978A
Other languages
Japanese (ja)
Inventor
Takanori Tagashira
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15850978A priority Critical patent/JPS5585913A/en
Publication of JPS5585913A publication Critical patent/JPS5585913A/en
Pending legal-status Critical Current

Links

Landscapes

  • Testing And Monitoring For Control Systems (AREA)

Abstract

PURPOSE:To enable to discriminate the defect in either of input and output section or external unit easily, and to diagnose the input and output section, by adding the high speed selector switch, level converter, and pattern generator and test input area. CONSTITUTION:When the failure diagnosis of input and output section 5 is desired, high speed switches 23, 24, 26, 27 are connected to T1, T2, T3, T4 side. Thus, the signal from the pattern generator 22 is inputted to the test input area 29 via the output buffer 11, transistor 12, fuse 13, level converter 25, and input buffer 15. When the pattern generator 22 outputs ''0'' state, it is inputted to the ''0'' state area 30, and when the ''1'' state is outputted, it is inputted to the ''1'' area 31, thus the high speed selection switch E32 is selected. Thus, when the input and output section 5 is correctly operated, the content of the test areas 30, 31 are respectively ''0'' and ''1''. If different, the input and output circuit of the input and output point is in failure.
JP15850978A 1978-12-25 1978-12-25 Sequence control unit Pending JPS5585913A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15850978A JPS5585913A (en) 1978-12-25 1978-12-25 Sequence control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15850978A JPS5585913A (en) 1978-12-25 1978-12-25 Sequence control unit

Publications (1)

Publication Number Publication Date
JPS5585913A true JPS5585913A (en) 1980-06-28

Family

ID=15673280

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15850978A Pending JPS5585913A (en) 1978-12-25 1978-12-25 Sequence control unit

Country Status (1)

Country Link
JP (1) JPS5585913A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57189209A (en) * 1981-05-12 1982-11-20 Oki Electric Ind Co Ltd Process input and output device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57189209A (en) * 1981-05-12 1982-11-20 Oki Electric Ind Co Ltd Process input and output device

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