JPS5585955A - Data processor - Google Patents

Data processor

Info

Publication number
JPS5585955A
JPS5585955A JP15742178A JP15742178A JPS5585955A JP S5585955 A JPS5585955 A JP S5585955A JP 15742178 A JP15742178 A JP 15742178A JP 15742178 A JP15742178 A JP 15742178A JP S5585955 A JPS5585955 A JP S5585955A
Authority
JP
Japan
Prior art keywords
instruction
address
operand
operands
control section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15742178A
Other languages
Japanese (ja)
Other versions
JPS5750296B2 (en
Inventor
Naoki Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15742178A priority Critical patent/JPS5585955A/en
Publication of JPS5585955A publication Critical patent/JPS5585955A/en
Publication of JPS5750296B2 publication Critical patent/JPS5750296B2/ja
Granted legal-status Critical Current

Links

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  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE: To speed up the exclusive logical sum ×C (Exclusive OR Character) instruction processing in which the operand addresses are mutually equal, by detecting the equal operand address in forecast, before the calculation and comparison of two operand addresses.
CONSTITUTION: The instruction read out ahead the execution of instruction is set to the instruction register 1. The base register numbers B1, B2 for address of the first and second operand of the register 1 and the address displacement parts D1, D2 are given to the comparison circuit 6. As the result of comparison in the circuit 6, if in agreement, the readout of the first and second operands is not made and all 0 data are fed to the memory unit access control section 7 and the instruction execution control section 8. If no agreement detection is made at the circuit 6, the data in the first and second operands are conventional registers via the selection circuits 4, 5, the output is added at the address adder 3, and the control section 8 is started so that the result is stored in the first operand. Since the operands are compared before the address calculation, ×C instruction is executed in high speed.
COPYRIGHT: (C)1980,JPO&Japio
JP15742178A 1978-12-22 1978-12-22 Data processor Granted JPS5585955A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15742178A JPS5585955A (en) 1978-12-22 1978-12-22 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15742178A JPS5585955A (en) 1978-12-22 1978-12-22 Data processor

Publications (2)

Publication Number Publication Date
JPS5585955A true JPS5585955A (en) 1980-06-28
JPS5750296B2 JPS5750296B2 (en) 1982-10-26

Family

ID=15649256

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15742178A Granted JPS5585955A (en) 1978-12-22 1978-12-22 Data processor

Country Status (1)

Country Link
JP (1) JPS5585955A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6246094U (en) * 1985-09-09 1987-03-20

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS511041A (en) * 1974-06-21 1976-01-07 Fujitsu Ltd
JPS51109743A (en) * 1975-03-22 1976-09-28 Hitachi Ltd

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS511041A (en) * 1974-06-21 1976-01-07 Fujitsu Ltd
JPS51109743A (en) * 1975-03-22 1976-09-28 Hitachi Ltd

Also Published As

Publication number Publication date
JPS5750296B2 (en) 1982-10-26

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