JPS558663A - Signal delay circuit - Google Patents

Abstract

PURPOSE: To delay input signals with a good S/N by mixing and delaying a control signal, which is modulated according to the level, etc., of input signals, and input signals which are made into a fixed level.

CONSTITUTION: The level of input signals is detected by level detection circuit 2, and a control signal which has the amplitude modulated according to the level of input signals is generated from voltage control amplifier 4 where output signals of carrier generation source 5 are applied. Input signals which are made into a prescribed level by voltage control amplifier 1 controlled by this control signal are mixed with modulation control signals, which are outputted from amplifier 4, through HPF 3 by mixer circuit 6, and these mixed signals are delayed by multistage bucket brigade device (BBC) 4. In this case, since input signals applied to device 4 are adjusted into a fixed level, S/N is not degraded even if small-level input signals are subjected to a long-time delay. As a result, when the delay output of element 4 is separated by HPF 8 and BFP 9 to adjust the level of delay input signals to the same level as an input time through voltage control amplifier 10, delay input signals with a good S/N can be obtained.

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