JPS5587201A - Double system controller - Google Patents

Double system controller

Info

Publication number
JPS5587201A
JPS5587201A JP16040978A JP16040978A JPS5587201A JP S5587201 A JPS5587201 A JP S5587201A JP 16040978 A JP16040978 A JP 16040978A JP 16040978 A JP16040978 A JP 16040978A JP S5587201 A JPS5587201 A JP S5587201A
Authority
JP
Japan
Prior art keywords
controller
controllers
output
input signal
state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16040978A
Other languages
Japanese (ja)
Inventor
Tadashi Nishijima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP16040978A priority Critical patent/JPS5587201A/en
Publication of JPS5587201A publication Critical patent/JPS5587201A/en
Pending legal-status Critical Current

Links

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  • Safety Devices In Control Systems (AREA)

Abstract

PURPOSE: To continue the timing of an output signal for more than a certain time even if two controllers constituting a double system would get out of period, by providing logic circuits between two controllers.
CONSTITUTION: Between controllers 3 and 4, logic circuit 12 is provided which is supplied with state output signal 10 of controller 3 and then outputs state input signal 11 to controller 4. In addition, logic circuit 15 is also provided which receives state input signal 13 of controller 4 and outputs state input signal 14 to controller 3. Those double-system controllers input a state output signal output by one controller to the other controller, and consequently output signals of controllers 3 and 4 definitely, so that even if the both would get out of period, the timing of two output signals can be continued for more than a certain time.
COPYRIGHT: (C)1980,JPO&Japio
JP16040978A 1978-12-25 1978-12-25 Double system controller Pending JPS5587201A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16040978A JPS5587201A (en) 1978-12-25 1978-12-25 Double system controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16040978A JPS5587201A (en) 1978-12-25 1978-12-25 Double system controller

Publications (1)

Publication Number Publication Date
JPS5587201A true JPS5587201A (en) 1980-07-01

Family

ID=15714305

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16040978A Pending JPS5587201A (en) 1978-12-25 1978-12-25 Double system controller

Country Status (1)

Country Link
JP (1) JPS5587201A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5741704A (en) * 1980-08-26 1982-03-09 Toshiba Corp Sequence controller
JPS5752902A (en) * 1980-09-12 1982-03-29 Hitachi Ltd Output collation system for digital controller
JP2013195026A (en) * 2012-03-22 2013-09-30 Panasonic Corp Cooker

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5741704A (en) * 1980-08-26 1982-03-09 Toshiba Corp Sequence controller
JPS5752902A (en) * 1980-09-12 1982-03-29 Hitachi Ltd Output collation system for digital controller
JP2013195026A (en) * 2012-03-22 2013-09-30 Panasonic Corp Cooker

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