JPS5587311A - Pcm-system signal recorder/reproducer - Google Patents

Pcm-system signal recorder/reproducer

Info

Publication number
JPS5587311A
JPS5587311A JP16545278A JP16545278A JPS5587311A JP S5587311 A JPS5587311 A JP S5587311A JP 16545278 A JP16545278 A JP 16545278A JP 16545278 A JP16545278 A JP 16545278A JP S5587311 A JPS5587311 A JP S5587311A
Authority
JP
Japan
Prior art keywords
signal
counter
dropout
free
running
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16545278A
Other languages
Japanese (ja)
Inventor
Kengo Sudo
Taizo Sasada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP16545278A priority Critical patent/JPS5587311A/en
Publication of JPS5587311A publication Critical patent/JPS5587311A/en
Pending legal-status Critical Current

Links

Landscapes

  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)

Abstract

PURPOSE: To prevent the evil effect of the dropout to the generation of the reading clock by producing the reading clock through the fixed free-running circuit.
CONSTITUTION: Vertical synchronous signal Sb isolated from the reproduced PCM video signal receives the delay of a fixed time via V delay circuit F, and then signal Sc equivalent to start signal Sd isolated through delay circuit A is generated. Thus even if signal Sd lacks due to the dropout or the like, signal Sc resets H counter G via OR circuit E. As a result, counter G has the free running via oscillator C to generate the reading clock with no evil effect given by the dropout, thus securing the assured reading for the fixed number of the data groups. The free-running counter G is stopped via V counter H and others after counting the fixed number of the data groups.
COPYRIGHT: (C)1980,JPO&Japio
JP16545278A 1978-12-23 1978-12-23 Pcm-system signal recorder/reproducer Pending JPS5587311A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16545278A JPS5587311A (en) 1978-12-23 1978-12-23 Pcm-system signal recorder/reproducer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16545278A JPS5587311A (en) 1978-12-23 1978-12-23 Pcm-system signal recorder/reproducer

Publications (1)

Publication Number Publication Date
JPS5587311A true JPS5587311A (en) 1980-07-02

Family

ID=15812682

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16545278A Pending JPS5587311A (en) 1978-12-23 1978-12-23 Pcm-system signal recorder/reproducer

Country Status (1)

Country Link
JP (1) JPS5587311A (en)

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