JPS5589998A - Data input unit - Google Patents

Data input unit

Info

Publication number
JPS5589998A
JPS5589998A JP16320078A JP16320078A JPS5589998A JP S5589998 A JPS5589998 A JP S5589998A JP 16320078 A JP16320078 A JP 16320078A JP 16320078 A JP16320078 A JP 16320078A JP S5589998 A JPS5589998 A JP S5589998A
Authority
JP
Japan
Prior art keywords
memory
input unit
test
counter
capacity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16320078A
Other languages
Japanese (ja)
Inventor
Takeo Tamada
Tomonobu China
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP16320078A priority Critical patent/JPS5589998A/en
Publication of JPS5589998A publication Critical patent/JPS5589998A/en
Pending legal-status Critical Current

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  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To establish the input unit easy for the confirmation of capacity of IC memory, by testing the memory and displaying the final address in response to the memory capacity.
CONSTITUTION: The input data in response to the operation of data key 1 is stored in the IC memory 3 via the processor 2 and displayed in the display section 6 via the selector 4 and register 5. When this input unit is at memory test mode with the operation of the function key 7, the address counter 9 is advanced with the test signal from the memory test circuit 8, the test data from the circuit 8 is stored in the address location of the memory 3 indicated with the counter 9 and the test data is displayed in 6 via the circuit 8, selector 4 and register. When this test is finished, the advancement of the counter 9 is stopped, and the final address from the counter 9 corresponding to the capacity of the memory 3 is similarly displayed to the unit 6 to establish the input unit easy for the confirmation of memory capacity of IC memory.
COPYRIGHT: (C)1980,JPO&Japio
JP16320078A 1978-12-27 1978-12-27 Data input unit Pending JPS5589998A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16320078A JPS5589998A (en) 1978-12-27 1978-12-27 Data input unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16320078A JPS5589998A (en) 1978-12-27 1978-12-27 Data input unit

Publications (1)

Publication Number Publication Date
JPS5589998A true JPS5589998A (en) 1980-07-08

Family

ID=15769174

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16320078A Pending JPS5589998A (en) 1978-12-27 1978-12-27 Data input unit

Country Status (1)

Country Link
JP (1) JPS5589998A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62124688A (en) * 1985-11-26 1987-06-05 Canon Inc information processing equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62124688A (en) * 1985-11-26 1987-06-05 Canon Inc information processing equipment

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